Dual Metal Double Gate Tunnel Research Articles

Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor

In this study, channel potential for silicon-based doped dual-metal double-gate tunnel field-effect transistor structure is analytically solved using the evanescent-mode approach in the sub-threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length λ which depends on tunnel current and does not depend along a transverse direction within the channel. The model is valid for the whole device structure rather than just semiconductor/insulator interfaces. The impact of variation of bias condition on channel potential is also investigated in the sub-threshold region. Finally, drain current is evaluated using Kane's and Kleysh's model and validated with a calibrated simulation, which has been carried out using 2D TCAD Sentaurus simulator.

Investigation of Ge based double gate dual metal tunnel FET novel architecture using various hetero dielectric materials

In this manuscript, Ge based dual metal double gate Tunnel Field Effect Transistor device has been investigated to overcome the challenges in conventional Si based TFET. This device gives a better drive current and an average Subthreshold slope using Ge channel. The performance analysis is done for various values of doping concentration and also for different hetero dielectric materials. It has very low leakage current (9.27 × 10−13 A/μm), a high on current (1.3 × 10−4 A/μm), giving an average Subthreshold slope of 34 mV/dec. This shows the device is better suitable for low power applications.

Dual metal-double gate tunnel field effect transistor with mono/hetero dielectric gate material

In this paper, dual metal-double gate tunnel field effect transistor (DMG-DGTFET) is discussed for mono & hetero dielectric gate material. The hetero dielectric that we have used at the gate is a combination of SiO$$_{\text{2 }}$$2 and HfO$$_{\text{2 }}$$2. The DMG technique is used to optimize the performance of DGTFET along with the mono/hetero dielectric gate material. The results obtained from the simulation are discussed using energy band diagram, tunneling barrier width and compared with hetero & mono dielectric gate. With the application of hetero dielectric to the DMG-DGTFET, the advantages of both the techniques combine and the results shows that higher $$I_{ON} /I_{OFF}$$ION/IOFF ratio $$(2\times 10^{9})$$(2×109) compared to the mono dielectric case $$(2.5\times 10^{8})$$(2.5×108). The average subthreshold slope also improves from 58 mV/decade in mono dielectric to 48 mV/decade in hetero dielectric DMG-DGTEFT. All the simulations are done in Synopsys TCAD for a channel length of 25 nm using the non-local tunneling model.