Dual-loop Frequency Synthesizer Research Articles

A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS

In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency varies for the channel selection according to the IEEE802.11aj (45 GHz) standard. The power hungry high-speed prescaler (or multi-modulus-divider) is replaced with a mixer in Loop2, thus the in-band phase noise and DC power consumption can be improved. The dual-loop dual-output synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 2.7 mm × 2.4 mm, and consumes 610 mW DC power. Measured results show the phase noise of the frequency synthesizer are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are observed during the measurement. To the best of our knowledge, this work is the first reported dual-loop dual-output synthesizer designed for IEEE802.11aj (45 GHz) standard.

고주파용 소형 저 위상잡음 주파수 합성기 설계에 관한 연구

In this paper, we designed low phase noise frequency synthesizer with compact size for High frequency band (Ku-band). The paper addresses merits and demerits of single loop and dual loop frequency synthesizer. The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed model in this paper more accurately predicts the low phase noise frequency synthesizer with compact size for high frequency band.

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.

A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers

A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.50-/spl mu/m CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm/sup 2/ and consumes a low power of 34 mW. The measured phase noise of the synthesizer is -121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels are -79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively.