Dual-loop Design Research Articles

Equilibrium optimiser tuned frequency-shifted internal model control proportional-derivative decoupled dual-loop design for industrial plants followed by experimental validation

Integrating and unstable processes require rugged control demand by virtue of their non-self-regulation character. The occurrence of system poles located at the origin and on the right half of the complex frequency plane causes instability in an open-loop configuration. When these processes proceed with dead time, it demands more sophisticated control requirements. Therefore, binal-loop control schemes are recommended over single-loop controller schemes. For plants with prevalent unstable and integrating dynamics and dead time, a novel modified inferred internal model control-proportional derivative decoupled binal-loop control system is suggested. The inner-loop is controlled by the stabilising proportional derivative controller with Routh–Hurwitz stability constraints. The outer-loop contains an inferred internal model controller for reference-point tracking. The equilibrium optimiser is then used to minimise the integral squared error by tuning the inner and outer-loop controller settings in the confined search space. The suggested strategy delivers appreciable enhancement in the quantitative performance measures as compared to some of the contemporary control techniques. The effect of time-varying disturbance and robust stability analysis is also presented. Finally, utilising a magnetic levitation laboratory setup, the suggested method is experimentally verified using the hardware-in-loop method.

Plasma nitrogen fixation system with dual-loop enhancement for improved energy efficiency and its efficacy for lettuce cultivation

Plasma nitrogen fixation (PNF) has been emerging as a promising technology for greenhouse gas-free and renewable energy-based agriculture. Yet, most PNF studies seldom address practical application-specific issues. In this work, we present the development of a compact and automatic PNF system for on-site agricultural applications. The system utilized a gliding-arc discharge as the plasma source and employed a dual-loop design to generate from air and water under atmospheric conditions. Experimental results showed that the system with a dual-loop design performs well in terms of energy costs and production rates. Optimal operational parameters for the system were determined through experimentation, resulting in an energy cost of 13.9 MJ mol−1 and an energy efficiency of 16 g kWh−1 for production, respectively. Moreover, the concentration of exhausted NO x was below the emission standards. Soilless lettuce cultivation experiments demonstrated that produced by the PNF system could serve as liquid nitrate nitrogen fertilizer. Overall, our work demonstrates the potential of the developed PNF system for on-site application in the production of green-leaf vegetables.

Compact photonic crystal multichannel drop filter for CWDM systems

A novel photonic crystal channel drop filter (PCCDF) is proposed to drop four coarse wavelength division multiplexing (CWDM) channels at 1490 nm, 1510 nm, 1530 nm and 1550 nm. A special coupled dual-loop design was used for multichannel forward/backward dropping for the first time. Due to the reduced number of the dropping resonators with this design, the proposed multichannel PCCDF has a very compact size (338 μ m2). High transmission efficiencies at the four ITU wavelengths (87.87%, 93.99%, 85.40% and 84.24%) can be obtained simultaneously. Furthermore, the same dimension parameters (lattice constant and rod radius) of the dual-loop resonators are helpful for easy fabrication. The proposed device could be used in future photonic integrated circuit-based CWDM communication systems.

Timing Recovery for Backplane Ethernet

The dominant solutions for single-chip multi-port backplane Ethernet transceivers utilize a dual-loop design - a combination of a single master phase-locked loop (PLL) and multiple slave delay-locked loops (DLL). Each transmitter or receiver port has its own DLL, which delays or advances a copy of the master clock from the master PLL to generate its own clock signal for synchronization. The DLLs are typically implemented using current-mode logic phase interpolators. This paper presents an alternative solution to this synchronization problem. Instead of moving the sampling phase, timing recovery is done by changing the group delay of the receiver-side forward equalizer by rotating its tap coefficients. The standard least-mean-square algorithm is used for coefficient rotation. This solution is equivalent to a first-order PLL/DLL, which suffers from steady-state timing offset when there is a frequency offset between the transmitter and the receiver. However, the degradation in performance caused by a frequency offset is significantly reduced by using a coefficient-rotation digital-signal processor capable of detecting and reducing the offset. With a practical frequency accuracy specification of plusmn100 ppm, the improved performance can approach that of the PLL/DLL dual-loop solution.

UPS inverter design using discrete-time sliding-mode control scheme

This paper presents a novel discrete-time sliding-mode control algorithm for an uninterruptible power supply (UPS) inverter design. The approach offers a dual-loop design, in which a current predictor utilizes the tracking error of output voltage to estimate the desired inductor current, while a current controller is adopted to regulate the inductor current and, thus, produces a control command to the pulsewidth modulation inverter. An explicit condition for stable controller design is derived. The efficacy of this scheme is validated via a successful implementation on a digital-signal-processor-based UPS inverter. The proposed scheme has shown its robustness on low output voltage distortion, excellent voltage regulation, and it is insensitive to load variation, even under nonlinear loads. Experimental studies were performed to further validate the effectiveness of this scheme.

Timing variation in dual loop benchmark

Benchmarks that measure time values using a standard system clock often employ a dual loop design. One of the important assumptions of this design is that textually identical loop statements will take the same amount of time to execute. This assumption has been tested on two bare computers with Ada® test programs and has been demonstrated to be inaccurate in these specific test cases.

Loading compensation for dual-loop feedback designs using inverted amplifiers

Low-gain dual-loop designs, using signal-inverting forward amplifiers, are shown to exhibit gain discrepencies due to feedback network loading. Gain correction is obtained by the addition of two resistors to a traditional dual-loop design.