Dual-gate Design Research Articles

(Invited) Organic Electrochemical Transistors for Marine Sensing

With our marine ecosystems under threat from climate change, there is an urgent need to continuously monitor marine conditions. One key indicator is the dissolved oxygen level, but existing sensors are limited by size and costs that preclude widespread non-intrusive monitoring. This work reports a new dual-gate design based on organic electrochemical transistors (OECTs) to track dissolved oxygen concentration in seawater, a highly challenging matrix owing to its high ionic strength and multitude of chemical interferents. We present the novel operating principle, by deriving the channel conductance with respect to potentials on the two gates. The dual-gate OECT was highly sensitive and stable compared to the conventional OECT structure, as the dual-gate configuration extended the device stability window by preventing undesirable reactions at the OECT channel. Specifically, the sensor achieved a detection limit of 0.5 ppm dissolved oxygen concentration in seawater. The device demonstrated reliable operation over five days and was capable of monitoring oxygenation changes arising from the photosynthesis cycles of saltwater macro-algae. In addition, we also engineer a system to monitor the correlation of oyster movement with dissolved oxygen in its environment, and it offers a new design to realize compact, highly sensitive, economical in-situ sensors for harsh marine environments.

Dual-gate design enables intrinsic safety of high-energy batteries

The safety issue hampers the application of high-energy lithium-ion batteries in electric vehicles, grid energy storage, electric ships and aircrafts. The chemical cross-talk, which refers to the migration of energetic intermediates between cathode and anode, initiates battery self-heating and accelerates the intensive heat release during battery thermal failure. However, blocking the chemical cross-talk is extremely hard. Previously, we may expect a thermally stable separator can guard the gate between battery cathode and anode, however, large amount of hot gas breaks the defense mechanically not thermally. Draining the cross-talk gas is of equal importance with blocking it. Herein, a dual-gate design notion is proposed, using separator as “block gate” and vent valve as “removal gate” to regulate the spatial distribution of energetic species to reduce the major heat release during battery thermal runaway. The design is validated by more than 50 battery chemistries. Typically, the maximum temperature of NMC811||Gr pouch cell decreases from >800 °C to <300 °C, the highest temperature rising rate decreases from 761.0 °C/s to 0.013 °C/s. The morphology and crystalline change of cathode verify that the chemical cross-talk is successfully suppressed. Moreover, such design has little side effect on the electrochemical performance of batteries. The dual-gate design breaks the bottleneck for the safety design of high energy batteries, providing insight into the safe utilization of electrochemical energy storage materials.

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC.

High-performance dual-gate graphene pH sensors

Field-effect transistors (FETs) are versatile tools for high-precision biophysical measurements, and their measurement sensitivity and resolution can be improved by using innovative materials and device designs. Here, we report on the sensitivity and noise performance of dual-gated graphene FETs. When measuring pH, our devices exhibit a sensitivity of up to 30 V per unit change in pH, ≈500-fold greater than the Nernst value at room temperature, and noise-limited resolution of 2 × 10−4 in the biomedically relevant 0.1–10 Hz bandwidth. This level of performance is obtained due to a highly asymmetric dual-gate design utilizing an ionic liquid top-gate dielectric coupled with graphene's large intrinsic quantum capacitance (≈15 μC/cm2). Our results improve upon the sensitivity and resolution of previously demonstrated Si- and MoS2-channel FET biosensors.

A new pressure microsensor based on dual-gate graphene field-effect transistor with a vertically movable top-gate: Proposal, analysis, and optimization

The combination of modern electronic devices and nanoelectromechanical systems (NEMS) has given new impulses to the development of sensors and biosensors. A new pressure microsensor based on graphene field-effect transistor (GFET) endowed with dual-gate design is proposed herein. The movable top-gate concept is used as sensing principle to detect the pressure-induced nanoscale displacement. A compact GFET drain-current model based on drift-diffusion carrier transport and field-effect principle is employed for the performance assessment of the proposed pressure microsensor. The investigation includes the top-gate and dual-gate configuration, transfer characteristic behavior, sensitivity analysis, operating regime, and the impact of gates' biases on the microsensor sensitivity. The performance analysis reveals that the dual-gate GFET design outperforms the top-gated GFET in terms of sensitivity. In addition, the high back-gate voltage and the low drain-source voltage have been found useful in improving the sensitivity of the DG GFET-based pressure sensor. Moreover, a metaheuristic optimization technique based on genetic algorithm (GA) has been adopted to find the optimal sensor parameters values that lead to the best sensitivity performance. The merits of the proposed dual-gate GFET-based pressure microsensor, namely small-size, high-sensitivity, graphene cost, and CMOS compatibility, make it a promising candidate for high-performance pressure sensing applications.

Device Characteristics of E-mode GaN HEMTs with a Second Gate Connected to the Source

In this study, the device characteristics of dual-gate GaN high-electron-mobility transistors (HEMTs) were determined. The research investigated an enhancement-mode (E-mode) GaN HEMT with a second gate connected to the source and located between the main gate and drain. Two dual-gate GaN HEMTs with different second-gate designs, using Schottky or metal–insulator–semiconductor (MIS) contacts, were simulated and fabricated, and the direct current of the devices was investigated. In device simulation, p-GaN gates were used to achieve E-mode operation in HEMTs. Technology computer-aided design (TCAD) simulation indicated that the saturation drain current (ID, sat) of devices with Schottky and MIS second gates was 88% and 38% lower than that of a single gate structure, while increasing on resistance (Ron) by 31% and 8%, respectively. In device fabrication, a Schottky and MIS second gate were respectively added to an E-mode p-GaN gate HEMT and an E-mode recesses-gate GaN MIS-HEMT. Compared with single-gate structures, the devices with a Schottky and MIS second gates reduced ID, sat by 75% and 32%, respectively, while increasing Ron by 25% and 6%, respectively. The measured electrical characteristics indicate the same trend obtained from TCAD simulation: The dual-gate design can improve the short-circuit capability of GaN HEMTs by reducing the ID, sat under on-state and high-current conditions.

Capacitive Spring Softening in Single-Walled Carbon Nanotube Nanoelectromechanical Resonators

We report the capacitive spring softening effect observed in single-walled carbon nanotube (SWNT) nanoelectromechanical (NEM) resonators. The nanotube resonators adopt a dual-gate configuration with both bottom-gate and end-gate capable of tuning the resonance frequency through capacitive coupling. Interestingly, downward resonance frequency shifting is observed with increasing end-gate voltage, which can be attributed to the capacitive softening of the spring constant. Furthermore, in-plane vibrational modes exhibit a much stronger spring softening effect than out-of-plan modes. Our dual-gate design should enable the differentiation between these two types of vibrational modes and open up the new possibility for nonlinear operation of nanotube resonators.

High-performance dual-gate carbon nanotube FETs with 40-nm gate length

We report on a high-performance back-gated carbon nanotube field-effect transistor (CNFET) with a peak transconductance of 12.5 /spl mu/S and a delay time per unit length of /spl tau//L=19 ps//spl mu/m. In order to minimize the parasitic capacitances and optimize the performance of scaled CNFETs, we have utilized a dual-gate design and have fabricated a 40-nm-gate CNFET possessing excellent subthreshold and output characteristics without exhibiting short-channel effects.

Reduction of gate current in AlSb/InAs HEMTs using a dual-gate design

Dual-gate AlSb/InAs HEMTs with 0.4 µm gate lengths have been fabricated, and exhibit a significant reduction in the gate leakage current associated with holes generated by impact ionisation. These HEMTs also have decreased output conductance and increased low frequency unilateral gain compared to single gate devices.

A new dual gate design for low current pulse operation in 16 Mb ion-implanted bubble memory devices

A design for a dual gate which has both pseudoswap and block-replicate functions for 16-Mb ion-implanted bubble memory devices has been proposed and shown by Sato et al. (1987) to reduce the operation current-pulse amplitude. The dual gate is composed of a pair of hair-pin conductor patterns in two layers and ion-implanted tracks for the major line and the minor loop corner. The current pulses are applied through the hair-pin conductor patterns to stretch, cut, or annihilate bubbles for the operation of the dual gate. The functions of the dual gate were realized with low current pulses of less than 150 mA using 0.8- mu m-diameter bubbles. It is therefore confirmed that the dual gate with low-current operation makes the 16-Mb ion-implanted bubble memory devices more practical. >