Dual Duty Cycle Research Articles

Selective productions of reactive species in dielectric barrier discharge by controlling dual duty cycle

AbstractThis study analyzes the selective productions of nitrogen oxides and ozone in dielectric barrier discharge due to temperature controlled by the dual duty cycle. In this work, we varied the dual duty cycle of the output voltage in the power supply, which alternatively generates distinguished high and low‐temperature modes for selective productions of nitrogen oxides and ozone. The alternating nitric oxide and ozone by dual duty cycle were measured at a maximum of 100 ppm and 100 ppm in the gas phase, respectively. In the evaluation of DI water treated by dual duty cycle, nitrogen oxides, and ozone have been observed simultaneously in the liquid phase. These results offer new insights into the selective production of temperature‐dependent chemical characteristics for advanced plasma applications.

A Photovoltaic-based Novel Transformerless High Gain Converter for DC Microgrid Applications

Aim: A typical microgrid network sourced by renewable energy encounters a technical setback owing to the voltage imbalance across the source integration and load power dissemination. Transformers employed to stabilize the potential may deteriorate the network efficiency and increases the cost and size of the system as well. Introduction: Photovoltaic based transformerless high gain DC-DC converter (THG-DC) is proposed here to aid the microgrid infrastructure. Microgrid fuelled by renewable energy sources demands the high gain converter interface to boost low voltage generation. The proposed THG-DC is employed with four switched inductors and three active power switches (IGBT) which are brought together under dual leg configurations. Methods: The proposed topology offers dual-duty cycle modes of regulating the active switches to realize the desired output voltage. Moreover, it is reliable to drive the proposed THG-DC with lower values of duty cycles to achieve a higher gain. The voltage stress across the switches is minimized and the magnitude of inductor current ripples is quashed to an extent. The proposed THGDC is simple in architecture and easy to control in all three operating modes. Results: The operating characteristics and performance investigation of the novel converter during the continuous and discontinuous modes are elucidated briefly and the comparative analysis on switching stress, gain, and efficiency are executed to justify the standards of the proposed THGDC. Conclusions: Finally, the miniature prototype model is experimented with in the laboratory (0.3 kW) and the obtained results are in agreement with the theory. It is evident from the investigations that the proposed THG-DC shows its dominance over other converters on the voltage gain, switching stress, number of components, and overall efficiency.

REVIEW OF ENERGY MINIMIZATION TECHNIQUES IN WIRELESS SENSORS NETWORK

The current decade of technology trends adopted the utilization of wireless sensors network. The wireless sensors network integrates with cloud based services and facilitate in every field of social engineering. The success story of sensors based network is utilization of energy. The sensor devices occupied tiny battery for energy. If the energy utilization is not maintained the life of network is expire. In this paper present the review of energy based protocol used in wireless sensor network. The maximum utilization of energy during the sensing of data of sensors node. Some authors used dual duty cycle for the sensing of sensor data and transmit data to sink node.

An Adaptive Energy-Management Framework for Sensor Nodes with Constrained Energy Scavenging Profiles

Modern energy harvesting systems for WSNs involve power scavenging sources, rechargeable batteries, and supercapacitors. Typical energy-management systems calculate/predict the remaining energy stored in a node, and associated actions are dispatched involving the networking protocols. However, long-term characteristics of the mentioned hardware components are typically neglected preventing the achievement of very long maintenance-free lifetimes (e.g., >5 years) for the nodes. In this work, a systematic analysis of this problem is provided, and an open energy-management framework is proposed which promotes (a) the nontraditional combination of primary cells, supercapacitors, and harvesting systems, (b) the concept of a distributed system inside a node, and (c) the adoption of the dual duty-cycle (DDC) operation for the WSNs. The DDC's core component is a cross-layer protocol implemented as an application-layer overlay which maintains the operation of the network under very high energy efficiency. Its trade-off is the reduction of the network throughput. Therefore, the DDC system has mechanisms that dynamically switch the WSN operational mode according to application's needs. Detailed guidelines are provided in order to allow the implementation of the solution on existing WSN platforms. The energy efficiency of the low duty-cycle mode of the solution is demonstrated by simulated and empirical results.

Design of a high-efficiency seven-port beam splitter using a dual duty cycle grating structure

In this paper, we propose a compact seven-port beam splitter which is constructed using only a single-layer high-density grating with a dual duty cycle structure. The properties of this grating are investigated by a simplified modal method. The diffraction efficiency can be achieved around 10% more than conventional Dammann gratings while the uniformity can still be maintained at less than 1%. The effect of deviations from the design parameters on the performance of the grating is also presented.

Unified all-digital duty-cycle and phase correction circuit for QDR I/O interface

A unified all-digital duty-cycle and phase correction circuit, consisting of dual duty cycle corrector loops and one shared control block, is proposed for a quadrature data rate I/O interface. The proposed scheme makes four duty-corrected and phase-corrected phase clocks from two clocks of 0deg and 90deg using the sequential three steps correction. The use of a newly devised duty cycle detector, which is digitally operated without external reference voltage, is proposed. With simulated results using 0.18 mum CMOS technology, the output duty cycle is corrected to 50plusmn0.4% as the input duty cycle ranges from 40 to 60%. The phase difference with the four-phase output clock is adjusted to 50plusmn0.6% (250plusmn3 ps) as the input phase-skew ranges from 40 to 60% (250plusmn50 ps) at a frequency of 1 GHz.

Unified all-digital duty-cycle and phase correction circuit for QDR I/O interface

A unified all-digital duty-cycle and phase correction circuit, consisting of dual duty cycle corrector loops and one shared control block, is proposed for a quadrature data rate I/O interface. The proposed scheme makes four duty-corrected and phase-corrected phase clocks from two clocks of 0deg and 90deg using the sequential three steps correction. The use of a newly devised duty cycle detector, which is digitally operated without external reference voltage, is proposed. With simulated results using 0.18 mum CMOS technology, the output duty cycle is corrected to 50plusmn0.4% as the input duty cycle ranges from 40 to 60%. The phase difference with the four-phase output clock is adjusted to 50plusmn0.6% (250plusmn3 ps) as the input phase-skew ranges from 40 to 60% (250plusmn50 ps) at a frequency of 1 GHz.

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI AC circuit while achieving high-speed operation. The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay. Ronmiddot tuning further improves the voltage and time margin by adding a user-supplied offset to auto-calibrated Ronmiddot. In addition, a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs. Measured results show that DBI DC coding reduces the peak-to-peak jitter from 65.5 ps to 44.5 ps and the voltage fluctuation from 183 mV to 115 mV at the data rate of 4 Gb/s with the 2 V.