Dual Data Rate Research Articles

Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA

Convolutional neural network (CNN)-based object detection has achieved very high accuracy; e.g., single-shot multi-box detectors (SSDs) can efficiently detect and localize various objects in an input image. However, they require a high amount of computation and memory storage, which makes it difficult to perform efficient inference on resource-constrained hardware devices such as drones or unmanned aerial vehicles (UAVs). Drone/UAV detection is an important task for applications including surveillance, defense, and multi-drone self-localization and formation control. In this article, we designed and co-optimized an algorithm and hardware for energy-efficient drone detection on resource-constrained FPGA devices. We trained an SSD object detection algorithm with a custom drone dataset. For inference, we employed low-precision quantization and adapted the width of the SSD CNN model. To improve throughput, we use dual-data rate operations for DSPs to effectively double the throughput with limited DSP counts. For different SSD algorithm models, we analyze accuracy or mean average precision (mAP) and evaluate the corresponding FPGA hardware utilization, DRAM communication, and throughput optimization. We evaluated the FPGA hardware for a custom drone dataset, Pascal VOC, and COCO2017. Our proposed design achieves a high mAP of 88.42% on the multi-drone dataset, with a high energy efficiency of 79 GOPS/W and throughput of 158 GOPS using the Xilinx Zynq ZU3EG FPGA device on the Open Vision Computer version 3 (OVC3) platform. Our design achieves 1.1 to 8.7× higher energy efficiency than prior works that used the same Pascal VOC dataset, using the same FPGA device, but at a low-power consumption of 2.54 W. For the COCO dataset, our MobileNet-V1 implementation achieved an mAP of 16.8, and 4.9 FPS/W for energy-efficiency, which is ∼ 1.9× higher than prior FPGA works or other commercial hardware platforms.

A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver Front-End for Energy-Efficient Dual-Rate Optical Links

This article presents a dual-bandwidth front-end (FE) for a rapidly reconfigurable dual data rate and power-proportional optical receiver. The proof-of-concept receiver FE is capable of operation at 8- and 4-Gb/s data rates. Implemented in 65-nm CMOS technology, the proposed FE consists of a shunt-feedback transimpedance amplifier (TIA), a configurable one-stage-to-three-stage postamplifier (PA), and an offset compensation (OC) loop. By reconfiguring the number of stages in the PA, the FE maintains a near-constant delay when its bandwidth is changed. This allows synchronization to be maintained, with limited bit errors when the target data rate is switched. The prototype receiver was measured with an optical input at 8 and 4 Gb/s. The overall FE dissipates 6.12 mW at 8 Gb/s (0.76 pJ/bit) and 2.86 mW at 4 Gb/s (0.72 pJ/bit). The measured receiver optical sensitivities for 8- and 4-Gb/s inputs at high-bandwidth (HBW) and low-bandwidth (LBW) modes are −7.7 and −9.8 dBm, respectively. The measurement results confirm the matched delay through the FE with delay variations within 8 ps.

Design of Low Power C Element Based Dual Data Rate Flip Flip

Fulfillment of dual edge flip-flops gets freshly develops into the goal of countless exploration to sustain expressive accomplishment of digital schemes while compressing power expenditure. Powerful low-power flip-flops acquire absolute basic district elements Gross sudden width of histrionic organizes successive circumferences / circuits. Conclude individually and remarkable testing as long as their vulnerability, Q-Delay, Rise Time Path, Fall Time Path and Average Power Consumption. While Power reveals smart effective count regarding the latest electrifying circuit transistors, uncertainly we survive balancing, including scheming comic numbers such as transistors that suspense each number of flip-flops. Analysis / inquiry on static / stable circuits is performed by Dual Data Rate (DDR) using PTM CMOS-16 nm technology alongside 5MHZ frequencies, including their victory procedure. Sensational Dual Data Rate (DDR) Flip-Flop uses 30% less capacity / power, including 14% lower C-Q delay. This paper's proposed architecture is to analyze logic size, area, and power consumption using tanner tool.

A Precise High Count-Rate FPGA Based Multi-Channel Coincidence Counting System for Quantum Photonics Applications

Coincidence counters play the role of gating events from the background noise in almost every quantum photonics setup. Precise multi-channel and high count-rate coincidence counting tools have become desirable due to an increase in the complexity of quantum photonics experiments. However, timing analyzers are struggling to meet these needs. We are proposing a Field Programmable Gate Array (FPGA) based coincidence counting system which provides 8 operational channels with 8.9 ps root mean square (RMS) resolution (with a bin width of 7.7 ps) and a count-rate of 320 million counts per second (MCPS) (with 40 MCPS per channel). We have successfully tested our design in different quantum photonics scenarios such as the detection of two-photon interference and pseudo-photon-number resolving detection of a coherent state of light where it has shown its capability of working beyond the saturation of detectors. Also, we have introduced a Dual Data Rate Registration TDC, which improved the linearity of the time tagging operation by using both clock edges without increasing the dead-time or using the space excessively. 1.2 LSB in max DNL error, 1.8 LSB in max INL error, 10 ps in FWHM and 3.2 ps in RMS resolution improvements were achieved.

HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers

This paper describes HighwayNoC, a Network-on-chip (NoC) that approaches ideal network performance using a Dual Data Rate (DDR) datapath. Based on the observation that routers datapath is faster than control, a DDR NoC allows flits to be routed at DDR improving throughput to rates defined solely by the datapath, rather than by the control. DDR NoCs can use pipeline bypassing to reduce packet latency at low traffic load. However, existing DDR routers offer bypassing only on in-network, non-turning hops to simplify the required logic. HighwayNoC extends bypassing support of DDR routers to local ports, allowing flits to enter and exit the network faster. Moreover, it simplifies the DDR switch allocation and the interface of router ports reducing power and area costs. Post place and route results in 28 nm technology show that HighwayNoC performs better than current state of the art NoCs. Compared to previous DDR NoCs, HighwayNoC reduces average packet latency by 7.3-27% and power consumption by 1-10%, without affecting throughput. Compared to existing Single Data Rate NoCs, HighwayNoC achieves 17-22% higher throughput, has similar or up to 13.8% lower packet latency, and mixed energy efficiency results.

Fault Tree Analysis To Understand And Improve Reliability Of Memory Modules Used In Data Center Server Racks

This research focuses on understanding the reliability of an important component of data servers and cloud computing, namely, Dual Data Rate (DDR4) devices in a Dual In-line Memory Module (DIMM) format. Data centres have thousands of DIMMs installed causing large failure rate. A failure to any component of these DDR4 DIMMs can cause operating issues for servers. A DIMM is a Printed Circuit Board Assembly (PCBA) with DDR4 devices that are surface mounted along with resistors, capacitors, a register, and an EEPROM chip. A literature review has shown that Fault Tree Analysis (FTA) does not appear to have been utilized to analyse DIMM failures. As such, this paper proposes an FTA methodology for use in DDR4 DIMM failure analysis. In an effort to validate this methodology, it is demonstrated by Fault Tress developed for three major failure modes observed. For identifying the root causes for these failure modes, various testing tools and techniques have been utilized to perform Root Cause Analysis (RCA) on 809 DDR4 DIMMS. Based on these RCA data, qualitative and quantitative analyses have been performed. Though this RCA/FTA approach is utilized to analyse memory modules found in data centres, the approach can be applied to analyse and predict failures and defect causes for highly automated manufacturing systems.

BodyWire: A 6.3-pJ/b 30-Mb/s −30-dB SIR-Tolerant Broadband Interference-Robust Human Body Communication Transceiver Using Time Domain Interference Rejection

Human body communication (HBC) utilizes the human body as the communication medium between devices in and around the body, providing an energy-efficient, secure alternative to radio wave communication traditionally used in body area networks (BAN). However, the human antenna effect results in the human body picking up environmental interference affecting HBC transmissions. Most state-of-the-art HBC transceivers utilize narrowband modulation techniques to communicate using frequencies, which are not affected by interference. In this article, we use capacitive termination and voltage mode communication techniques to utilize the human body as a broadband (BB) communication channel enabling as a BB HBC. An integrating dual data rate (I-DDR) receiver utilizing time-domain interference rejection (TD-IR) through integration and periodic sampling is used for interference-robust BB HBC operation. The proposed receiver can achieve higher energy efficiency as it utilizes the full bandwidth of the body for data transmission and does not require any modulation/demodulation. The BB HBC transceiver is fabricated in the TSMC 65-nm technology. Measurement results show 6.3-pJ/bit energy efficiency at a data rate of 30 Mb/s with -30-dB signal-to-interference ratio (SIR) tolerance, making it 18× energy efficient compared with state-of-the-art HBC transceivers.

Theoretical Analysis of AM and FM Interference Robustness of Integrating DDR Receiver for Human Body Communication.

Prolific growth of miniaturized devices has led to widespread use of wearable devices and physiological sensors. The state-of-art technique for connecting these devices and sensors is through wireless radio waves. However, wireless body area wireless body area network (WBAN) suffers from limited security (wireless signals from energy-constrained sensors can be snooped by nearby attackers), poor energy-efficiency (up conversion and down conversion), and self-interference. Human body communication (HBC), which uses human body as a conducting medium, has emerged as a new alternative physical layer for WBAN, as it can enable communication with better energy efficiency and enhanced security. Broadband (BB) HBC uses the human body channel as a broadband communication medium and can enable higher energy efficiency compared to narrowband HBC. However, due to the antenna effect of human body, ambient interferences get picked up from the environment, proving to be one of the primary bottlenecks for BB-HBC systems. In this paper, we analyze the performance of an integrating dual data rate (I-DDR) receiver, which enables interference robust BB-HBC, under continuous wave (CW), amplitude modulated (AM), and frequency modulated (FM) interferences. Theoretical derivations along with simulations provide key insights into the behavior of I-DDR receiver under different interference scenarios, highlighting the efficacy (>22dB improvement in SIR tolerance for both FM and AM) of the technique. Finally, measurements are carried out by applying the I-DDR principle on signals transmitted through the human body and captured on an oscilloscope. Measurements from an I-DDR receiver fabricated in TSMC 65nm technology shows <10-4 BER in presence of CW, AM, and FM interference with -21dB SIR further demonstrating the efficacy of the I-DDR method in interference rejection.

High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.

DDRNoC

This article introduces DDRNoC, an on-chip interconnection network capable of routing packets at Dual Data Rate. The cycle time of current 2D-mesh Network-on-Chip routers is limited by their control as opposed to the datapath (switch and link traversal), which exhibits significant slack. DDRNoC capitalizes on this observation, allowing two flits per cycle to share the same datapath. Thereby, DDRNoC achieves higher throughput than a Single Data Rate (SDR) network. Alternatively, using lower voltage circuits, the above slack can be exploited to reduce power consumption while matching the SDR network throughput. In addition, DDRNoC exhibits reduced clock distribution power, improving energy efficiency, as it needs a slower clock than a SDR network that routes packets at the same rate. Post place and route results in 28nm technology show that, compared to an iso-voltage (1.1V) SDR network, DDRNoC improves throughput proportionally to the SDR datapath slack. Moreover, a low-voltage (0.95V) DDRNoC implementation converts that slack to power reduction offering the 1.1V SDR throughput at a substantially lower energy cost.

High speed FPGA-based data acquisition system

An application that involves high speed signal changes at input side makes it very important to have a high speed Data Acquisition without loss of any data. This paper discusses FPGA design architecture programed by VHDL firmware which involves high speed Analog to digital converter (ADC) with sampling rate of 80 mega samples per second, Direct Memory Access (DMA) programed in such a way which transfers data without loss of single data sample and high speed Dual Data Rate 3 (DDR3) SDRAM to store digitized data for further manipulations. It also describes data-rate, and speed achieved to transfer data and plot a graph of digital value which shows there is no loss of data.

Designing of Soft Core Processor System with Direct Memory Access (DMA) Mode

A soft core processor system is constructed using embedded design techniques and it is configured on Field Programmable Gate Arrays (FPGAs). The system is accommodated to act with Direct Memory Access (DMA) mode using suitable Xilinx Intellectual Property (IP) core. A dual data rate synchronous dynamic random access memory (DDR_SDRAM) with 64 Mbyte capacity is introduced to the system and accessed by the DMA controller.The controller is performed to transfer programmable quantity of data from source address to destination address without intervention of the processor. Spartan-3E slice is used and programmed using Xilinx Platform Studio (XPS)which is provided by Xilinx integrated software environment at (ISE 10.1). The system performance is tested by transferring data from matlab media to the DDR_SDRAM and vice-versa, mat lab 2012a version software is used for this type of data transfer.

C-slow retimed parallel histogram architectures for consumer imaging devices

A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

ATCA/AXIe compatible board for fast control and data acquisition in nuclear fusion experiments

An in-house development of an Advanced Telecommunications Computing Architecture (ATCA) board for fast control and data acquisition, with Input/Output (IO) processing capability, is presented. The architecture, compatible with the ATCA (PICMG 3.4) and ATCA eXtensions for Instrumentation (AXIe) specifications, comprises a passive Rear Transition Module (RTM) for IO connectivity to ease hot-swap maintenance and simultaneously to increase cabling life cycle.The board complies with ITER Fast Plant System Controller (FPSC) guidelines for rear IO connectivity and redundancy, in order to provide high levels of reliability and availability to the control and data acquisition systems of nuclear fusion devices with long duration plasma discharges.Simultaneously digitized data from all Analog to Digital Converters (ADC) of the board can be filtered/decimated in a Field Programmable Gate Array (FPGA), decreasing data throughput, increasing resolution, and sent through Peripheral Component Interconnect (PCI) Express to multi-core processors in the ATCA shelf hub slots. Concurrently the multi-core processors can update the board Digital to Analog Converters (DAC) in real-time. Full-duplex point-to-point communication links between all FPGAs, of peer boards inside the shelf, allow the implementation of distributed algorithms and Multi-Input Multi-Output (MIMO) systems. Support for several timing and synchronization solutions is also provided.Some key features are onboard ADC or DAC modules with galvanic isolation, Xilinx Virtex 6 FPGA, standard Dual Data Rate (DDR) 3 SODIMM memory, standard CompactFLASH memory card, Intelligent Platform Management Controller (IPMC), two PCI Express x4 (generation 2) ATCA Fabric channels (dual-star topology), eleven Xilinx Aurora x1 (or other ATCA compatible communications protocol) ATCA fabric channels (full-mesh topology) and two Fast Ethernet (Precision Time Protocol – PTP IEEE1588-V2 and Lan eXtensions for Instrumentation – LXI compatible) ATCA base channels (dual-star topology).