Dual Damascene Interconnects Research Articles

Analysis of Electromigration in Dual-Damascene Interconnect Structures

The effects of grain boundaries on electromigration failure are presented. The electromigration model incorporates the grain boundary as a separate medium which acts not only as fast diffusivity path for material transport but also absorbs and releases vacancies. Moreover, we analyze the void nucleation condition and its implication on electromigration failure is discussed. Our results show that high stress and a high vacancy concentration develop at the triple points formed on the interface between copper grains and the capping layer, where a void nucleation is likely to take place. This scenario of weak triple points in combination with a stress threshold also supports the mechanism of multiple void nucleation as it has been experimentally observed.

(Invited) Alternative Metals for Beyond-Cu Interconnects

In recent technology nodes, interconnect scaling has become a major bottleneck for the reduction of the area of CMOS circuits. In the near future, interconnect dimensions will reach 10 nm and below. Reducing the cross-sectional area of interconnect wires and vias increases their resistance and consequently degrades the performance of the circuit. This geometrical effect is aggravated by an increased resistivity of the conductor metal, Cu, due to enhanced surface and grain boundary scattering. Moreover, it becomes increasingly difficult to ensure the reliability of scaled Cu interconnects. Barrier layers, such as TaN, are required to limit diffusion into the surrounding dielectrics. Resistance to electromigration is reduced in small dimensions, which can be mitigated e.g. by Co liners. However, both barriers and liners reduce the volume available for Cu while contributing little to the line conductance.These issues have recently led to an increased research for alternatives to the current Cu dual damascene interconnect technology. Materials innovation is a key to mitigate the reduction of interconnect performance. An ideal conductor metal allows for reliable interconnect operation without requiring barrier or liner layers, thus maximizing the available conductor volume. Moreover, it possesses a lower sensitivity to surface and grain boundary scattering than Cu, which means that the resistivity degrades more gradually with reduced interconnect line width. This property can be linked to a smaller mean free path of the charge carriers with respect to Cu (~40 nm) and thus metals with short mean free paths have been of particular interest.To identify suitable alternative conductor metals, we have developed a staged approach, which is schematically represented in the figure. Ab initio calculations of the product of the bulk resistivity and the mean free path as a figure of merit [1,2] are used to shortlist potential candidate metals. While a short mean free path indicates a weak sensitivity to finite size effects of the resistivity due to enhanced surface and grain boundary scattering, a low bulk resistivity is of equal importance to ensure a low resistivity at small dimension. By contrast, the cohesive energy (or the melting point) of a metal can be used as proxies for its expected electromigration performance and the need for barrier layers. This approach has now been applied to all relevant elemental metals as well as many binary and some ternary intermetallics. As concerns elemental metals, Co, Mo, as well as the Pt-group metals show particularly promising behavior. We will also review the situation for binary and ternary intermetallics.In a next step, thin film experiments have been used to assess the performance of the shortlisted metals experimentally. We will show that in particular several Pt-group metals show lower resistivities than Cu for ultrathin films with thicknesses below 10 nm. In addition, opportunities and challenges of binary or ternary intermetallics with respect to elemental metals will be discussed. In a third step, scaled interconnect wires of different alternative metals have been fabricated using a metal spacer process based on ion-beam etching [3-5]. The results indicate that Co, Ru, Ir, and Rh show promise to outperform Cu in narrow dimensions. Calibrated compact models of the line resistance indicate that the main gain in resistance over Cu interconnect lines and vias stems from the increased conductor volume since no barrier and line layers are required for reliable operation with a smaller contribution of the reduced resistivity. Finally, the remaining challenges in the integration of alternative metals in scaled interconnects are discussed.[1] D. Gall, J. Appl. Phys. 119, 085101 (2016).[2] S. Dutta, K. Sankaran, K. Moors, G. Pourtois, S. Van Elshocht, J. Bömmels, W. Vandervorst, Z. Tőkei, and C. Adelmann, J. Appl. Phys. 122, 025107 (2017).[3] L.G. Wen, et al., ACS Appl. Mater. Interfaces 8, 26119 (2016).[4] S. Dutta, S. Kundu, A. Gupta, G. Jamieson, J.F. Gomez Granados, J. Bömmels, C.J. Wilson, Z. Tőkei, and C. Adelmann, IEEE Electron Dev. Lett. 38, 949 (2017). Figure 1

Evaluation of Hybrid Bonding Interface Quality by Contact Resistivity Measurement

With the rise of hybrid bonding as a solution for fine pitch 3-D integration, new methods are required to evaluate the bonding quality at a wafer level. Contact resistance is widely used for process control but measurements can be corrupted by the 3-D stack complexity and the misalignment of wafers. In order to measure the specific contact resistivity of dual-damascene interconnects and evaluate the Cu/Cu bonding interface, 3-D cross Kelvin resistors (3-D CKRs) have been specially designed. Electrical characterizations and complementary simulations demonstrate that test structures are functional if the specific contact resistivity is higher than $10^{-{8}}\,\,\Omega \cdot \textsf {cm}^{{2}}$ . Despite bonding defects evidenced by morphological characterization, the specific contact resistivity remained below the measurement limit. The good reconstruction of Cu/Cu interface does not allow contact resistance measurement.

Experimenting and modeling of catastrophic failure in electromigration-induced resistance degradation for deep submicron dual-damascene copper interconnects

The features of electromigration-induced resistance change profile are important aspects of reliability, especially for ULSI interconnect. By experimenting on 0.28 µm wide Cu dual-damascene interconnects, clear evidence of catastrophic failure is observed even when the failure criterion of only 2% resistance change is imposed. Applying theoretical constitutive law of degradation and using basic principles of generic model, constitutive equation for resistance degradation in electromigration is derived and simulated for catastrophic failure. Then real-time resistance change profile is obtained by a simple analytical model which incorporates the Nernst-Einstein relation of mass transport. The convergence of the analytical model to the generic one is also shown. The various aspects of catastrophic failure are discussed. A good correlation between the results obtained from the model and experiment are shown.

Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method

Electromigration effects are a key failure mechanism for copper-based dual damascene interconnects wires in semiconductor technologies. However, accurately predicting the time-to-failure for a complicated interconnect tree in a VLSI interconnect layout requires detailed knowledge of the stress evolutions over time, and is subject to time-varying currents and temperature. This is a challenging problem as one needs to solve the stress-based partial differential equations (PDEs) in the time domain for confined copper damascene interconnect trees for both void nucleation and void growth phases. To mitigate this problem, we propose a novel Krylov subspace-based method for fast numerical solutions to the stress PDEs. The new approach, which we call FastEM , is based on the finite-difference method which is used to first discretize the PDEs into linear time-invariant ordinary differential equations (ODEs). After discretization, a modified Krylov subspace-based reduction technique is applied in the frequency domain to reduce the size of the original system matrices so that they can be efficiently simulated in the time domain. The FastEM can perform the simulation process for both void nucleation and void growth phases under piecewise constant linear current density inputs and time-varying stressing temperatures. Furthermore, we show that the steady-state response of stress diffusion equations can be obtained from the resulting ODE system in the frequency domain, which agrees with the recently proposed voltage-based EM analysis method for EM immortality checks. Numerical results show that the proposed method can lead to about 1–2 orders of magnitude speed-up over existing finite-difference time-domain-based methods on large interconnect trees for both void nucleation and growth phases with negligible errors. We further show that for most of the interconnect trees tested; we only need a small number of dominant poles for sufficient accuracy.

Fabrication of an ultra-thin low resistance and high stability Ru–Mo–C seedless barrier for advanced Cu dual-damascene interconnects

Cu dual-damascene interconnects with an amorphous Ru–Mo–C (labeled as RuMoC) seedless barrier layer were successfully fabricated and its feasibility for advanced Cu dual-damascene interconnects were investigated. The results show that the RuMoC II films obtained with sputtering rates (Ru:MoC) of 100:50 demonstrated the best performance, exhibiting an amorphous structure, low residual oxygen content, low resistivity at temperatures up to 500 °C. A Cu plug of good quality was successfully electroplated on the RuMoC II barrier layer with 4-nm-thick without seed layer in a damascene structure. The ultra-thin RuMoC II barrier effectively blocked the diffusion of Cu and O atom after being annealed up to 500 °C. The damascene structure showed much lower leakage current and via resistance compared to the damascene structures with traditional Ta barrier, suggesting that RuMoC II film has sufficient barrier properties. Moreover, the via resistance of the damascene structures with RuMoC II barrier were quite low and met the requirement of different technology nodes for the future semiconductor industry, indicating great prospects for advanced seedless Cu metallization applications.

Etching Feasibility of CoWP and CoWB as Selective Metallic Capping Layer in Cu Dual Damascene Interconnection

Etching Feasibility of CoWP and CoWB as Selective Metallic Capping Layer in Cu Dual Damascene Interconnection

Investigation of microstructure and properties of ultrathin graded ZrNx self-assembled diffusion barrier in deep nano-vias prepared by plasma ion immersion implantation

Ultrathin graded ZrNx self-assembled diffusion barriers with controllable stoichiometry was prepared in Cu/p-SiOC:H interfaces by plasma immersion ion implantation (PIII) with dynamic regulation of implantation fluence. The fundamental relationship between the implantation fluence of N+ and the stoichiometry and thereby the electrical properties of the ZrNx barrier was established. The optimized fluence of a graded ZrN thin film with gradually decreased Zr valence was obtained with the best electrical performance as well. The Cu/p-SiOC:H integration is thermally stable up to 500°C due to the synergistic effect of Cu3Ge and ZrNx layers. Accordingly, the PIII process was verified in a 100-nm-thick Cu dual-damascene interconnect, in which the ZrNx diffusion barrier of 1nm thick was successfully self-assembled on the sidewall without barrier layer on the via bottom. In this case, the via resistance was reduced by approximately 50% in comparison with Ta/TaN barrier. Considering the results in this study, ultrathin ZrNx conformal diffusion barrier can be adopted in the sub–14nm technology node.

Characterization of Ultra Thin Copper Layers

Abstract The technological progress of microelectronic devices is directly coupled with the ability to produce transistor circuits and interconnects on the wafer level with increasingly small dimensions while providing equal or even better electrical properties and functionality. Therefore every new generation of microchip manufacturing is a challenge for the existing production technologies to compete with the raised requirements as well as for the material scientific methods to characterize and control the properties of the incorporated dielectrics and deposited metal layers with dimensions in the nm range. The following article will illustrate the investigation methods that have been applied for the development of electrolessly plated copper layers of less than 3 nm thickness to provide a conductive copper seed for subsequent copper electroplating to fill Dual Damascene interconnects of the 14 nm or 10 nm technology node. The methods used are AFM, Ellipsometry, 4-point resistivity, XPS, EELS, XRF, XRD, FIB/HR-STEM, HR-TEM.

A Novel Bottom up Fill Mechanism for the Metallization of Advanced Node Copper Interconnects

A new alkaline copper plating bath enabling a unique and innovative bottom up effect for advanced damascene and dual damascene interconnect metallization is described. The formation of an ultra-stable polynuclear copper(I) complex during the early stage of the deposition process inhibits copper reduction, leading to a very strong suppressing effect. Bottom up growth is then achieved by means of selective breakdown of the suppressing layer from the bottom to the top of the features without any accelerator additive.

The Development of Cu Filling and Reliability Performance with Ru-Ta Alloy Barrier for Cu Interconnects

Ru-Ta alloy was investigated as the diffusion barrier layer in Cu dual damascene interconnects, and Cu filling property and reliability performances with RuTa/RuTa(N) stacked barrier structure were mainly evaluated. RuTa strongly orientated to Ru(002) and the lattice misfit between Ru(002) and Cu(111) was lower than that between Ta(110) and Cu(111). The wettability of Cu seed on RuTa was much better than that on Ta. The barrier property against Cu diffusion of RuTa/RuTa(N) stacked barrier structure kept the equivalent barrier property of conventional Ta/TaN one. Filling property of Cu electroplating was improved by using Ru-Ta alloy barrier, and trenches of 45 nm in width could be filled successfully due to the suppression of the agglomeration of Cu seed on the sidewall of trench. Via resistance with RuTa/RuTa(N) barrier was much lower than that with Ta/TaN one due to its low resistivity. The estimated life time of via electromigration with RuTa/RuTa(N) barrier was longer than that with Ta/TaN one because of the good wettability and filling property inside via. Consequently, Cu filling property and reliability performance can be improved with RuTa/RuTa(N) stacked barrier structure in Cu interconnects.

ALD TaN Barrier for Enhanced Performance with Low Contact Resistance for 14nm Technology Node Cu Interconnects

We report on an alternative, atomic layer deposited (ALD) TaN barrier scheme for Cu interconnects for 14nm technology node and beyond, i.e., 64nm pitch and/or smaller interconnects. With VLSI integration requiring denser packing of interconnects, conformal fill of progressively narrower trenches and vias with high aspect ratio, presents tough challenge for line-of-sight physical vapor deposition processes. ALD overcomes these gap-fill challenges but has disadvantages of low throughput, chemical residues and relatively lower density of ALD barriers for effective blocking of O2and Cu diffusion. From gap-fill perspective, ALD films enable ultrathin, conformal barrier with reduced problems of overhang and large bottom thickness, typical of physical vapor deposited (PVD) films. Reduced bottom-thickness enables via-contact resistance reduction and less overhang improves gap-fill, while maximizing Cu volume in a trench/via structure. Our blanket film studies show that ALD films are 10-15% less dense compared to Ta-rich PVD films, and more importantly only desired low-resistance alpha-Ta nucleates on ALD films vs. thin PVD films. The conformality of ALD TaN as well as the nucleation of alpha-Ta on it form the basis of via contact resistance reduction, leading to performance enhancement.A plasma-enhanced ALD (PEALD) process helps increase density and improves the hermeticity of the barrier. But PEALD can cause dielectric damage and lead to TDDB failures especially in smaller technology nodes. To maximize density while protecting low-k dielectric during deposition and maintaining low-contact resistance, we explored different flavors and combinations of thermal (tALD) and plasma-enhanced ALD (PEALD). In this work, we use a new, commercially available 40 MHz direct-plasma ALD tool and corresponding optimized processes to maximize throughput and minimize dielectric damage. Different ALD flavors, viz., tALD+post plasma(PP) treatment, tALD/PEALD bilayer films were evaluated for 14 nm technology groundrule interconnects in k=2.7 and k=2.55 dielectric levels. We were able to achieve via contact resistance reduction of 25-35%, with equivalent or better performance for yield, defectivity and electromigration (EM), time-dependent dielectric breakdown (TDDB) and stress migration (SM) reliability. In-line measured defect density for dual-damascene interconnects in k=2.55 dielectric was studied with a conservative ALD TaN thickness process window; the splits with 15-20A of tALDPP TaN barrier layers were found to have the lowest defectivity. Similar data for various ALD splits vs. PVD showed that the same tALDPP process with a certain thickness combination of the bilayer TaN/ Ta resulted in least defect density. This same optimized condition looked best for viachain yield for a macro with ~108via links at 14nm groundrule. We also confirmed that the same condition resulted in the lowest via contact resistance for fully landed vias for 45 chiplets across 3 wafers; where via bottom size variation was <10%. Another study with several bilayer ALD splits in k=2.55 dielectric, showed that the 5tALD/5PEALD condition with initial tALD layer protecting the low-k dielectric followed by denser PEALD to get a more effective barrier, yielded better than PVD TaN. The lowest via resistance data was also recorded for the same split. The EM stress results for both via and line-depletion at each of k=2.7 and k=2.55 levels were also studied. ALD splits were slightly worse than PVD condition with the exception of one stress direction, but still pass reliability targets scaled from the 22 nm technology node. The kinetics data for via depletion tests results in activation energy in excess of 1 eV. TDDB stress results were obtained for builds in both k=2.7 and k=2.55 dielectrics. The most significant impact of ALD on TDDB was the restoration of voltage acceleration parameter (gamma) for both levels. Gammas (slopes of lines) for ALD of all three devices were clearly higher. This confirmed that our optimized ALD condition does no damage to the dielectric. Lastly, impact of different liner processes on stress migration (SM) was investigated at 225oC stress for 1000 hours. There were no stress fails on any of the liner splits from the traditional plate and nose type SM structures. In summary, ALD TaN is shown to be a robust alternative barrier for Cu interconnect technology for technologies nodes like 14nm and smaller. The process can be optimized to give ~30% reduction in via contact reduction while preserving healthy yield, defect density and EM, TDDB and SM reliability.

Ultrahigh Purity Copper Alloy Target Used Innanoscale ULSI Interconnects

Current ULSI circuits have features with dimensions in the nanoscale region. As the critical dimension shrinks, Cu BEOL systems face reliability impacts. Alloying has been proved to be a promising technique to retard grain boundary electro-migration (EM). In this paper, dilute Cu Alloys such as Cu-Al, Cu-Mn for dual-damascene interconnect applications have been investigated. The alloy chosen principle for nanoscale interconnects has been discussed. The ultrahigh purity copper alloy target properties including purity, alloy composition, grain size and sputtering performance were investigated, to lay the foundation for the application of the large-size ultrahigh purity copper alloy target used for 300mm wafer fabrication. The relationships between deposited film behaviors and sputtering target properties in some applications were also discussed. In order to acquire high quality thin film, the properties of sputtering target such as alloy composition homogeneity, grain size and uniformity et al. have to be well controlled by proper fabrication techniques.

The contact resistance reduction of Cu interconnects by optimizing the crystal behavior of Ta/TaN diffusion barrier

Ta/TaN bi-layer films, commonly used as diffusion barriers in Cu interconnects, have been deposited by self-ionized plasma system with various plasma conditions in this study. The variations of TaN compositions are revealed by secondary ion mass spectrometer. The structural properties of Ta/TaN films have been systematically investigated by X-ray diffraction patterns and transmission electron microscopy. On amorphous TaN film with low N concentration, Ta film consists of α-phase Ta (α-Ta) and β-phase Ta (β-Ta). The sheet resistance of Ta film with the mixture of α-Ta and β-Ta is decreased by the expansion of α-Ta content. The formation of pure α-Ta film can be achieved by increasing the N concentration of underlying amorphous TaN film. For α-Ta film, the enlargement of grain size can reduce the sheet resistance. In the practical application of Ta/TaN diffusion barrier, Kelvin contact resistance of Cu dual damascene interconnects is successfully reduced by the combination of α-Ta film with enlarged grains and amorphous TaN film with high N concentration.

ALD and PVD Tantalum Nitride Barrier Resistivity and Their Significance in via Resistance Trends

As dual damascene interconnects are scaled down to sub-30nm critical dimension (CD), the patterning processes required are highly complex, and metallization processes, beyond providing void-free Cu fill, need to address the resistance challenges encountered [1]. In terms of scaled barriers, suitable PVD Ta(N) and ALD TaN processes need to be identified for acceptable barrier performance as well as for their impact on interconnect resistance. For example, enhancing nitrogen content in PVD TaN may enable Cu barrier thickness scaling without a reduction in its barrier properties.In order to evaluate the impact of nitrogen content in TaN on resistivity, various PVD TaN processes were developed based on Ar/N2 DC sputtering from a Ta target. While maintaining a fixed Ar flow rate, both DC sputtering power and N2 flow rate were varied to allow deposition of TaN films with a particular nitrogen content. Four-point probe sheet resistance measurements were performed to determine TaN resistivity, while the composition of TaN was determined by Rutherford back-scattering spectrometry (RBS). For comparisons to PVD TaN, PEALD TaN processes, based on the reduction of pentakis(dimethylamino)tantalum (PDMAT) with either a H2 plasma or an NH3 plasma, were utilized in this study.Limiting the N2 flow rate while sputtering TaN is one of the most commonly adopted strategies to avoid N contamination of PVD Ta, resulting in typical PVD TaN resistivity values of approximately 200-250 μΩcm. When the N2 flow rate during PVD of TaN is significantly increased, a stark trend in TaN resistivity is observed [2]. For example, under fixed Ar flow rate and DC sputtering conditions at 15kW, TaN resistivity is observed to change from ~270 μΩcm to more than 1600 μΩcm as the N2 flow rate is increased from 40 to 50 sccm (Figure 1). For comparison, typical resistivity values of ALD TaN are on the order of ~5000 μΩcm or higher, although high-power plasma reduction or ion bombardment steps can reduce ALD TaN resistivity to ~500 μΩcm [3].Sputtering at a reduced TaN deposition rate (e.g., by applying low DC power) is expected to allow more nitrogen incorporation into TaN. Composition analysis of the PVD TaN films studied indeed confirms that, at fixed N2 flow rate, 15kW DC TaN with a resistivity of ~240 μΩcm contains only ~26 at.% N, while 6kW DC TaN with a resistivity of ~550 μΩcm contains ~48 at.% N (Figure 2). Typical N content in ALD TaN based on PDMAT is ~50 at. % or higher, which is likely related to the Ta-N bond structure in the precursor molecule.Both ALD TaN and PVD TaN barrier processes were compared in terms of their impact on Cu dual damascene via resistance. A test structure with 40nm-wide vias was constructed for this purpose. For an ALD TaN barrier at 3nm thickness, the via resistance measured was ~28% lower than its PVD counterpart (Figure 3). Given the blanket ALD TaN resistivity (~5000 μΩcm) and PVD TaN resistivity (~240 μΩcm) values for these barrier processes, it is apparent that other factors besides blanket TaN resistivity play a role in the total via resistance observed. It is likely that TaN nucleation differences, interface cleanliness, via test structure geometry, a.o. also need to be taken into account.This work was performed by the Research and Development Alliance Teams at various IBM Research and Development Facilities. REFERENCES S.T. Chen, T.-S. Kim, S. Nam, N. Lafferty, C.-S. Koay, N. Saulnier, H. Shobha, W. Wang, Y. Xu, B. Duclaux, Y. Mignot, M. Beard, Y. Yin, H. Shobha, O. Van der Straten, M. He, J. Kelly, M. Colburn, T. Spooner, Proc. IEEE International Interconnect Technology Conference (IITC) 2013, pp. 1-3 (2013).S.-M. Na, I.-S. Park, S.-Y. Park, G.-H. Jeong, S.-J. Suh, Thin Solid Films 516, 5465 (2008).P. Ma, J. Lu, J. Aubuchon, T.-J. Gung, M. Chang, ECS Trans. 33 (2), 169 (2010).

Effect of layout on electromigration characteristics in copper dual damascene interconnects

This study demonstrates that the electromigration (EM) behavior of dual damascene Cu lines is strongly affected by the layout which surrounded the tested EM lines, especially for Cu line below 0.10μm used for 40nm or below technologies. The Cu EM lifetime declines as the number of local dummy lines increase, and the global dummy line density increases with the width of the Cu line below 0.063μm. This work presents mechanisms of layout effects that explain the EM characteristics and can be exploited to improve the layout effect. Therefore, not only the stressed Cu line structures, but also the surrounding layouts must to be considered in assessing EM reliability of a real IC circuit in 40nm or below technology.

Interface characterization and evaluation of the reactive preclean process for the removal of Cu oxide in the Cu nanointerconnect process

To fabricate a reliable device using Cu interconnect technology, it is important to form an initial pattern profile with a good sidewall surface roughness at via bottom due to barrier step coverage issues. However, if Ar sputter etch clean is used at via contact clean prior to barrier deposition, this induces a Cu redeposition on the via sidewall. This redeposited Cu can lead to the degradation by sidewall morphology and finally the reliability issues due to poor barrier step coverage. In this study, we evaluate the reactive preclean process (RPC) as an alternative technology to overcome the disadvantages of sputter clean and discuss the effectiveness of RPC on the removal of Cu oxide in Cu dual damascene interconnect.

PVD Cu Reflow Seed Process Optimization for Defect Reduction in Nanoscale Cu/Low-k Dual Damascene Interconnects

A novel Cu reflow seed process which utilizes physical vapor deposition (PVD) technology components has been demonstrated for nanoscale dual damascene interconnects. Prior to Cu electroplating, small features can be partially filled with Cu by this newly developed Cu reflow seed process. It is confirmed that both suitable seed coverage and appropriate reflow temperature are required for achieving ideal reflow property. Bias conditions during Cu PVD dominate seed coverage in features, and processes at moderate bias are demonstrated to provide optimum bottom and sidewall coverage, while limiting field coverage. Overall Cu fill performance was enhanced significantly and more than a 60% improvement in via-chain yield is obtained by Cu reflow seed compared to conventional seed. Furthermore, Cu lines with fewer voids and less impurities are fabricated by repeating this Cu reflow seed process several times to obtain complete feature fill, which results in lower leakage current between lines. This Cu reflow seed process is a promising candidate for improving Cu fill performance for nanoscale Cu/low-k interconnects of 32 nm critical dimension and beyond.

56 nm pitch Cu dual-damascene interconnects with self-aligned via using negative-tone development Lithography-Etch-Lithography-Etch patterning scheme

In the attempts to push the resolution limits of 193nm immersion lithography, this work demonstrates the building of 3 metal level 56nm pitch copper dual-damascene interconnects, using Negative-Tone Development Lithography-Etch-Lithography-Etch (LELE) Patterning at line level. Line Resistance and intra-level capacitance can be affected by the double patterning integration, but a good process window has been demonstrated, showing no impact on RC performance. The introduction of a self-aligned via (SAV) process with a TiN hard-mask is able to provide a robust process window in terms of via-metal short yield at line and via level. SAV implementation at these dimensions also affects the aspect-ratio of the structures and leads to new challenges in metallization: optimized profile, without bowing or undercut, is mandatory to enable the filling of 28nm lines. The metal hard-mask has to be removed or at least faceted by erosion. This can be achieved by conventional RIE process optimization, but pushes the RIE selectivity to challenging limits. Physical dimensions on target and via chain yield have been demonstrated by fine tuning RIE process. Profile improvement can also be achieved by the introduction of new WET process, helping the removal of the metal hard-mask while being neutral to the ULK. We have demonstrated good yield and reliability with an integration using hard-mask wet removal.

Effects of Low-kStack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Low capacitance and highly reliable Cu dual-damascene (DD) interconnects have been developed with self-organized "seamless low-k SiOCH stacks" (SEALS) structure. A carbon-rich sub-nano porous SiOCH (k=2.5) was directly stacked on an oxygen-rich porous SiOCH (k=2.7) in the SEALS structure, without a hard-mask (HM) and etch-stop (ES) layer of SiO2. The effective k-value (keff) of the Cu DD interconnect including the SiCN capping layer (k=4.9) was reduced to 2.9 compared to 3.4 on a conventional hybrid structure with SiO2-HM and ES, which had been used in 65-nm-node mass production. The interconnect delay of a 45-nm-node complementary metal oxide semiconductor (CMOS) ring oscillator (RO) was reduced by 15% referring to that of the conventional hybrid structure. Interconnect reliabilities, such as the interline time dependent dielectric breakdown (TDDB) and thermal cycles, were unchanged from those of the conventional hybrid interconnects. No failure was detected for chip package interaction (CPI) during reliability tests in a plastic ball grid array (PBGA) package. SEALS is a promising structure for scaled down ultra large scale integrations (ULSIs) for highly reliable and high speed operation, and low power consumption.