Dual-conversion Receiver Research Articles

Wireless Interrogation of Implantable SAW Sensors.

Implantable sensors provide long-term, accurate physiological measurements after a minimally invasive procedure, particularly when designed as transponders. Wireless interrogation of deeply implanted transponders with RF remains a challenge due to the high loss at the skin-air interface and large tissue RF absorption. This paper presents a system for wirelessly interrogating surface acoustic wave (SAW) sensors implanted in the main pulmonary artery (PA), where the pressure (PAP) is a very important parameter in the management of heart failure patients. The proposed PAP monitoring system consists of an implantable SAW pressure sensor integrated with an antenna and anchor in a housing, an external antenna and an electronic interrogator. The PAP is determined by measuring the frequency of the echo signal from SAW sensor accurately. An asymmetric antenna was designed and integrated with the sensor. The combination of simulation, theoretical calculation and phantom measurement indicates that the path loss to the implant location, about 6cm below the skin, is around 25dB. A portable interrogator was designed based on a dual conversion receiver and single echo high frequency sampling approach to assess achievable frequency estimation accuracy predicted by Cramer-Rao Lower Bound (CRLB) analysis. The system was characterized using a high quality (Q) factor SAW sensor, fabricated at wafer level, wire-connected to the interrogator via an attenuator to simulate path loss. The signal-to-noise ratio (SNR) of captured echo signals was calculated and used in CRLB analysis. The analysis indicates that without using signal post processing, the sensor sensitivity has to be at least 440Hz/mmHg in order to achieve a target 1mmHg accuracy. Although the current sensor sensitivity is only 200Hz/mmHg, the in vivo measurement showed that acceptable accuracy can be obtained by signal post processing. The results from an invasive catheter tip transducer measured simultaneously with the SAW sensor showed that the differences in pulse pressure and relative mean pressure are 0.8mmHg and 1.4mmHg, respectively. The accuracy could be further improved by increasing the sensor Q factor and sensitivity and reducing path loss.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

5/60 GHz $0.18~\mu m$ CMOS Dual-Mode Dual- Conversion Receiver Using a Tunable Active Filter for 5-GHz Channel Selection

A dual-mode dual-conversion receiver with two far-apart carrier frequencies, 5 and 60 GHz, and two very different channel bandwidths, tens-MHz and GHz, is demonstrated in a standard $0.18~\mu \text {m}$ CMOS technology. The dual conversion architecture receives 60-GHz mode using Schottky diodes at the first conversion stage and merges 5-GHz mode at the second conversion stage. The 5-GHz RF channel selection is achieved by inserting a 20-MHz bandwidth tunable active filter after a 5-GHz low-noise amplifier for the noise concern and before the second down-conversion mixer to relax the linearity requirement of subsequent stages. A tunable active filter with improved linearity using a transformer-coupled scheme is employed. As a result, the narrow 20 MHz channel bandwidth selection at 5-GHz mode shows a 500 MHz tuning range with noise figure of 9 dB and conversion gain of 28 dB. For 60-GHz operation, the 3-dB IF bandwidth is 1 GHz with noise figure of about 20 dB and conversion gain of −3 dB.

A MB-OFDM UWB 0.18-μm CMOS RF Front-End Receiver

An RF front-end dual-conversion receiver for <TEX>$3{\sim}5\;GHz$</TEX> MB-OFDM UWB systems is implemented in <TEX>$0.18\;{\mu}m$</TEX> CMOS technology. The receiver includes a two-stage UWB LNA, an RF mixer, an IF I/Q mixer, and a frequency synthesizer. The proposed receiver adopts the dual-conversion architecture to mitigate the burden of design of the frequency synthesizer. Accordingly, the proposed frequency synthesizer generates four LO tones from only one VCO. The receiver front-end achieves power gain of 16.3 to 21 dB, NF of 7 to 7.6 dB over <TEX>$3{\sim}5\;GHz$</TEX>, and IIP3 of -21 dBm, while consuming 190 mW from a 1.8 V supply.

A 12-GHz silicon bipolar dual-conversion receiver for digital satellite applications

A 12-GHz monolithic silicon bipolar receiver for digital video broadcasting via satellite (DVB-S) is presented. The receiver is based on a dual-conversion superheterodyne architecture that employs a single LO integrated in the same die. To comply with the stringent LO phase noise requirement of -101 dBc/Hz at 100 kHz offset from the carrier, an innovative VCO topology, based on a three-layer monolithic transformer, was used. The VCO exhibits a phase noise of -102 dBc/Hz at 100 kHz offset from a 5.3-GHz carrier and a 1.1-GHz tuning range. At 12 GHz, the conversion gain is 33.6 dB, the single-sideband noise figure is 5.9 dB and the output IP3 is +16 dBm. This work reports the first 12-GHz DVB-S monolithic receiver integrated in a low-cost silicon bipolar technology.

A 2.4 GHz low-IF receiver for wideband WLAN in 0.6μm CMOS

Abstract This paper presents the 2.4 GHz front-end and the first downconversion section of a fully integrated low-IF receiver. The dual-conversion receiver and rejects the image repeatably by 60 dB using integrated polyphase filters without calibration or tuning. The gain of the RF mixer and IF amplifier is switchable to slide the available dynamic range of the following stages, based on the conditions of the input signal. The front-end and downconversion sections drain 35 mA on average from a 3.3 V supply. Minimum cascade NF is 7.2 dB, and maximum cascade IIP3 is −3.4 dBm.

A 2.4-GHz low-IF receiver for wideband WLAN in 6-/spl mu/m CMOS-architecture and front-end

This paper presents the 2.4-GHz front-end and the first downconversion section of a fully integrated low-IF receiver. The dual-conversion receiver rejects the image repeatably by 60 dB using integrated polyphase filters without calibration or tuning. The gain of the RF mixer and IF amplifier is switchable to slide the available dynamic range of the following stages based on the conditions of the input signal. The front-end and downconversion sections drain 35 mA on average from a 3.3-V supply. Minimum cascade noise figure is 7.2 dB, and maximum cascade IIP3 is -3.4 dBm.

An integrated silicon bipolar receiver subsystem for 900-MHz ISM band applications

A wide-band dual conversion receiver subsystem is presented which is suitable for 900-MHz portable wireless applications including cordless telephony. The circuit features 118 dB of dynamic range and is operable from 6.5 V down through 2.7 V while consuming 26 mA. The receiver utilizes the MOSAIC V radio frequency (RF) silicon bipolar process and features an LNA, two mixers, two oscillators, second LO amplifier, dual modulus prescaler, LF amplifier, RSSI, coilless demodulator, and power down control.