DSP Memory Research Articles

Wide Voltage Input Full Bridge(FB)/Half Bridge(HB) Morphing-Based LLC DC–DC Converter Using Numerical Optimal Trajectory Control

Full-bridge/half-bridge (FB/HB) morphing topology is very suitable to be used in a wide input voltage range for an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> dc–dc converter. To improve the dynamic performance in facing the input voltage variation, a numerical optimal trajectory control is presented. The power circuit considering its parasitic parameters is simulated first and the simulated data can be stored in DSP memory. These discrete data can be used to obtain the accurate gain-frequency curve versus different loads by numerical methods. The proposed numerical optimal trajectory (OTC) can achieve a very fast and smooth transition between FB/HB in facing the input voltage variation. A 640 W 220–760 V input/400 V output <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> resonant converter is built. The effectiveness of the proposed numerical OTC has been verified by the simulation and experimental results.

An Analysis of a shutdown caused by a misoperation of differential protection of high-voltage auxiliary transformer

In response to an accident of misoperation of the high-voltage factory transformer differential protection, the cause of the misoperation was investigated and analyzed from the perspective of the volt-ampere characteristics of the current transformer and the protection operation information, and it pointed out the abnormal interruption of DSP memory caused by the malfunction of differential protection, and put forward the corresponding treatment and preventive measures.

DSP Memory Allocation Strategy Based on Greedy Algorithm

In practical applications of DSP systems, DSP chips with limited on-chip RAM resources are often chosen to reduce cost. In this condition, part of the codes has to be stored in FLASH or expanded RAM and thus can not run at full speed. This paper presents a strategy of allocating the on-chip RAMs to obtain the maximum system performance. First, the memory allocation problem is described as the knapsack problem, and then the greedy algorithm is applied. Experimental results show that the overall execution efficiency can be improved by 10% when the on-chip RAMs are rather limited. Therefore, the proposed memory allocation method is efficient for low-cost design to obtain higher performance.

A PSO based optimal switching technique for voltage harmonic reduction of multilevel inverter

Selected lower order harmonics of multilevel inverter are eliminated while the overall voltage THD is optimized by computing the switching angles using particle swarm optimization (PSO) technique. The discontinuity in the solution of selected harmonic elimination (SHE) problem at certain modulation indices is avoided by optimizing the individual harmonics to allowable limits. While choosing the set of solution leading to minimum THD, the abrupt changes in the switching angles are discarded by limiting the voltage THD within allowable limits. Also the selected higher order harmonics are eliminated by additional switching along with the lower order harmonics. In order to reduce the computational burden for online application, the switching angles computed by the proposed PSO technique for optimum THD at varying modulation indices are stored as a look-up table in the DSP memory. The simulated results are also validated through suitable experiments.

A Reprogrammable EDGE Baseband and Multimedia Handset SoC With 6-Mbit Embedded DRAM

A CMOS EDGE baseband and multimedia handset SoC features a dual core (microcontroller and DSP) architecture together with all the necessary interface logic and hardware accelerators interconnected by a multi-layer bus. The DSP memory hierarchy features an instruction cache coupled to a 6-Mbit embedded DRAM instruction memory allowing in the field software flexibility (for example dynamic upgrade of DSP software), while minimizing power and area (closely matching a ROM based solution). The chip is implemented in a 130-nm 6-metal layer CMOS process and is packaged in a 12 /spl times/ 12 ball-grid array. Full chip standby mode current is 690 /spl mu/A (with data retention), resulting in a 500 hour complete GSM/EDGE terminal autonomy.

Speech codec and a method of processing a speech signal with speech codec

One frame of speech signal data and subframes of speech signal data divided from the frame of speech signal data are encoded by frame and subframe encoding processes while another frame is decoded by frame and subframe decoding processes. The frame and subframe encoding processes and the frame and subframe decoding processes are interleaved to reduce the DSP memory capacity needed for a speech codec.