Drop Test Reliability Research Articles

ZrO2 Nanoparticle Embedded Low Silver Lead Free Solder Alloy for Modern Electronic Devices

In this article, the authors present the synthesis of Sn–1.0Ag–0.5Cu (SAC105) alloy embedded with zirconium oxide nanoparticles using simple mechanical blending and casting route. The cast samples were characterized in terms of microstructural evolution, wetting, microhardness, and drop test reliability. The characterizations were performed by using a tabletop X-ray diffraction, field emission scanning electron microscope, and the compositions were identified by energy dispersive spectroscopy. The results showed that addition of ZrO2 nanoparticles significantly refines the grain size, Ag3Sn, and Cu6Sn5 intermetallic compounds thickness by 46, 14, and 26% respectively as compared to the single component SAC105 alloy. The results were also compared with those of standard Sn–3.0Ag–0.5Cu (SAC305) alloy. Although the spreading and microhardness of SAC105 is found to be slightly poor or comparable to SAC305 yet drop test reliability can be improved significantly after addition of ZrO2 nanoparticles appreciably. This kind of refinement results in a cheap alternative to SAC305 with comparable mechanical strength and high solder joint reliability.

Ball impact responses of Sn-1Ag-0.5Cu solder joints at different temperatures and surface finishes

The purpose of this paper is to measure and analyze the Sn-1Ag-0.5Cu solder joints under high speed ball impact test (BIT) conditions. In this study, the ball impact test was conducted at impact velocity of 300 mm/s on package-level solder joints with 0.3 mm ball diameter, bonded individually on substrate pads of Ni/Au, OSP and Ni/Pd/Au surface finishes at elevated temperature of 25, 50, 75, 100 and 125 °C, respectively. The experimental results show that Ni/Pd/Au surface finish at room temperature has higher intermetallic compound (IMC) strength performance than Ni/Au and OSP. These three different substrate surface finishes, however, tend to have quite similar IMC strength performance at elevated operation temperature. The board-level drop test reliability of TFBGA 14 mm × 14 mm 409 L for these surface finishes were also performed at room temperature. The trends of BIT results are in good agreement to board-level drop test reliability. A three-dimensional finite element analysis (FEA) model was established to analyze the transient structural responses in the solder joint for determining the maximum impact toughness capacity. The effects of temperature on solder joint material yield stress and IMC strength on the impact characteristics were investigated.

MEMS Packaging Reliability in Board-Level Drop Tests Under Severe Shock and Impact Loading Conditions–Part I: Experiment

The continuing increase of functionality, miniaturization, and affordability of handheld electronic devices has resulted in a decrease in the size and weight of the products. As a result, printed wiring assemblies (PWAs) have become thinner and more flexible, and clearances with surrounding structures have decreased. Therefore, new design rules are needed to minimize and survive possible secondary impacts between PWAs and surrounding structures because of the consequential amplification in acceleration and contact stress. This paper is the first of a two-part series and focuses on the drop test reliability of commercial off-the-shelf microelectromechanical systems (MEMS) components that are mounted on printed wiring boards (PWBs). Particularly in this paper, we are interested in gaining preliminary insights into the effects of secondary impacts (between internal structures) on failure sites in the MEMS assemblies. Drop tests are conducted under highly accelerated conditions of 20 000 ${g}$ (“ ${g}$ ” is the gravitational acceleration). Under such high accelerations, the stress levels generated are well beyond those expected in conventional qualification tests. Furthermore, secondary impacts of varying intensities were allowed by changing the clearance between the PWB and the fixture. As a result, the stress and accelerations are further amplified, to mimic unexpected secondary impacts in a product if/when design rules fail to avoid such conditions. The amplification of the test severity is quantified by comparing the characteristic life ( $\eta $ in a Weibull distribution) of all the tested MEMS components at each clearance. Multiple failure sites from drop testing are identified, from packaging-level failures to MEMS device failures. The participation of competing failure sites is also demonstrated via characteristic life representations of each failure site at various clearances.

Board Level Drop Reliability of Epoxy-Containing Sn-58 mass% Bi Solder Joints with Various Surface Finishes

Board-level drop reliability testing under JEDEC (Joint Electron Device Engineering Council) drop conditions was conducted for low-temperature Sn-58 mass%Bi solder joints. The effects of surface finish and the number of reflow processes (one, three, or five) on the drop reliability of the Sn-58Bi joints were evaluated. Three types of surface finishes were used including electroless nickel immersion gold (ENIG), electroless nickel electroless palladium immersion gold (ENEPIG), and organic solderability preservatives (OSP). We successfully fabricated six types of drop test specimens with various surface finishes and bonding materials, and then performed the board-level drop tests. The board-level drop reliability was improved when using the composite Sn-58Bi solder with epoxy as compared to Sn-58Bi solder without epoxy. In addition, the reliability of the Sn-58Bi epoxy solder/OSP joint was better than both the ENIG and ENEPIG surface finishes. When the number of reflow processes increased, the drop reliability showed two different behaviors; specifically, the reliability of the ENIG and ENEPIG surface finishes decreased while the OSP surface finish improved. The existence of epoxy in the solder paste improved the drop reliability of the solder joints. After drop testing, cracks propagated differently with different surface finishes, namely between Ni3Sn4 IMCs and the Ni-P layer for the ENIG surface finish, between Ni3Sn4 IMCs and the solder bulk for the ENEPIG surface finish, and within the solder bulk for the OSP surface finish. These data show that, when it is necessary to perform repeated reflow processes for electronic components, solder joints with an OSP surface finish provide better drop test reliability results.

Effect of Electromigration on the Type of Drop Failure of Sn–3.0Ag–0.5Cu Solder Joints in PBGA Packages

Board-level drop tests of plastic ball grid array (PBGA) packages were performed in accordance with the Joint Electron Devices Engineering Council standard to investigate the effect of electromigration (EM) on the drop reliability of Sn–3.0Ag–0.5Cu solder joints with two substrate surface finishes, organic solderability preservative (OSP) and electroless nickel electroless palladium immersion gold (ENEPIG). In the as-soldered state, drop failures occurred at the substrate sides only, with cracks propagating within the interfacial intermetallic compound (IMC) layer for OSP solder joints and along the IMC/Ni–P interface for ENEPIG solder joints. The drop lifetime of OSP solder joints was approximately twice that of ENEPIG joints. EM had an important effect on crack formation and drop lifetime of the PBGA solder joints. ENEPIG solder joints performed better in drop reliability tests after EM, that is, the drop lifetime of ENEPIG joints decreased by 43% whereas that of OSP solder joints decreased by 91%, compared with the as-soldered cases. The more serious polarity effect, i.e., excessive growth of the interfacial IMC at the anode, was responsible for the sharper decrease in drop lifetime. The different types of drop failure of PBGA solder joints before and after EM, including the position of initiation and the propagation path of cracks, are discussed on the basis of the growth behavior of interfacial IMC.

Study on Board-Level Drop Impact Reliability of Sn–Ag–Cu Solder Joint by Considering Strain Rate Dependent Properties of Solder

Board-level drop reliability test and analysis require dynamic characterization of the high strain-rate properties of the solder, along with solder joint failure tests. Relying on just the drop impact analysis of board-level dynamic response (i.e. G-levels and board bending strains) and an oversimplification of deformation response of solder joints (i.e., assuming elastic stress criteria) can lead to misleading conclusions in the physics-of-failure understanding in drop impact tests. In this paper, impact tests were conducted with a split Hopkinson pressure bar test system to study the dynamic response of bulk solder materials. A finite-element analysis of drop impact was conducted by considering different solder constitutive models such as the elastic and strain rate-dependent plastic model to investigate the effect of the solder constitutive model on the dynamic response of the solder joint. The important finding of this study is that the constitutive model used has a major impact on the dynamic response of solder joint stress and strain results. Theoretically, it is predicted that the strain rate-dependent plastic model gave better correlation results than the simple elastic model. A solder joint reliability characterization using the drop impact test with a clamped–clamped boundary condition was investigated for a plastic ball grid array assembly with Sn–Ag–Cu solder and two board surface finishes. In order to assess drop reliability of solder joint with different surface finishes, Charpy test was conducted to evaluate the dynamic strength of the soldered specimen using Sn–Ag–Cu solder and with or without Ni/Au plating.

Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

3D FEM Simulations of Drop Test Reliability on 3D-WLP: Effects of Solder Reflow Residual Stress and Molding Resin Parameters

Numerous three-dimensional (3D) packaging technologies are currently used for 3D integration. 3D-wafer level package (3D-WLP) appears to be a way to keep increasing the density of the microelectronic components. The reliability of 3D components has to be evaluated on mechanical demonstrators with daisy chains before real production. Numerical modeling is acknowledged as a very efficient tool for design optimization. In this paper, 3D finite-elements calculations are carried out to analyze the effects of molding resin’s mechanical properties and thickness on the 3D component’s dynamic response under drop loading conditions. Residual stress generated by solder reflow is also discussed. The influences of residual stresses on the numerical estimation of the component behavior during drop loading are studied. Solder reflow residual stresses have an impact on solder plastic strain and die equivalent stress calculations. We have compared the result of two numerical drop test models. Stress-free initial conduction is introduced for the first model. Solder reflow residual stresses are considered as the initial condition for the second drop test model. Quantitative and qualitative comparisons are carried out to show the effect of residual stress in drop test calculations. For the effect of molding resin thickness on the component behavior under drop loading, the stress-free initial condition is considered. The effect of the molding resin’s thickness on critical area location is discussed. The solder bump maximum plastic shear strain and the silicon die maximum equivalent stress are used as reliability criteria. Numerical submodeling techniques are used to increase calculation accuracy. Numerical results have contributed to the design optimization of the 3D-WLP component.

Comparison study on reliability performance for polymer core solder balls under multiple reflow and HTS stress tests

Drop ball reliability for Ball Grid Array (BGA) package on lead-free product is a major reliability concern. Integrating a polymer core in the solder ball could be a good strategy to dissipate stress better compared to the purely metallic solder ball. However, the diffusion rate of the copper is much faster than the diffusion rate of the solder. Hence, Kirkendall voids starts forming and causing crack between the interface of copper and solder. This could affect the solder joint as well as the solder ball drop reliability especially when subjected to high temperature stress. The new polymer core solder ball with 1μm thickness of nickel (Ni) coated on the copper (polymer core/copper/nickel/solder) could offer better solder ball joint and drop reliability performance. This work studies the effects of IMC growth, solder ball shear strength and drop test reliability. Subsequently, the failure modes were observed after multiple reflow (up to 5 times) and HTS stress tests. The IMC formation was observed under the high power scope with magnification 50× via the mechanical cross-section and was measured using an analytical software tool. Solder ball shear test was carried out to measure the solder joint performance after multiple reflow and HTS stress tests via the Dage 4000 series bond tester. Drop reliability test was carried out via the packing drop test. From this study, we could conclude that the polymer core solder ball with an additional Ni layer coating demonstrates better performance than the polymer core solder ball without Ni layer. The same observation applies to the solder ball shear strength, drop reliability performance in multiple reflow and HTS stress tests. The IMC thickness for polymer core solder ball without additional Ni layer is much thicker than the polymer core solder ball with an additional Ni layer, most probably because Ni could limit the Cu diffusion into the solder, thus resulting in better reliability performance.

The Combined Effect of Shock Impacts and Operational Power Cycles on the Reliability of Handheld Device Component Board Interconnections

A compact high-density test board has been subjected to combinations of power cycling and shock impact loads. The test board was designed to replicate both the mechanical shock impact response and the thermomechanical response of a commercial handheld device component board under product- and board-level tests. The power cycling loading affected the microstructure of the solder interconnections by (1) enhancing the growth of interfacial intermetallic compound layers and (2) driving the coalescence of intermetallic particles inside the solder bulk. These microstructural changes initially improved drop test reliability, but longer exposure time caused the drop reliability to deteriorate. The lifetimes and failure modes of the test boards were found to be similar in concurrent and consecutive test combinations. Furthermore, the lifetime trend of the consecutive power cycling and drop tests was found to be the same in board- and product-level tests. This confirms that product-level reliability can be assessed with board-level tests.

Effect of the combination of surface finishes and solder balls on JEDEC drop reliability of chip-scale packages

► This study looks at ENEPIG, as it is paired with three solder compositions. ► Board-level chip-scale packages subjected to a JEDEC drop test. ► Sb, Ni and Pt were minor doped for enhancing strength and good wettability. ► The drop performances of ENEPIG are found better than those of Ni/Au. ► Most of the failure modes are on the test board side along the brittle interfaces. Cost reduction pressure has been amplified by the escalation of the price of gold. Reducing gold thickness is the only alternative in the hedge against such escalation but may compromise bondability and reliability. In order for a molten bond to exist between two metallic materials, the formulation of IMCs is inevitable. A bond too thick or too thin could harm the interface bondability or gold embrittlement respectively. In order to protect against such harm, the surface finish and solder must be considered. This study, therefore, looks at ENEPIG, a gold-reduction surface finish, as it is paired with three solder compositions: SAC125Sb, SAC125NiSb, and SAC105Pt. This investigation pairs these three components on board-level thin-profile fine-pitch ball grid array chip-scale packages and tests them with an industrial standard electroplated Ni/Au. Test performance is examined by a JEDEC drop reliability test.

Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages

Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes like thin die stacking, 8-in wafer encapsulation using compression molding, low-temperature dielectric with processing temperature less than 200°C have been developed. The EMWLP components success fully pass 1000 air to air thermal cycling (-40°C to 125°C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (>; 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q-factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL, and package thicknesses can lead to designs with improved mechanical reliability.

2nd Level Reliability Improvement on WLCSP

Recently the package market is demanding the smaller package size and the lower impedance electrical path with a short interconnection. The wafer level chip scale package is one of them, which has the solution of the market needs above. However, WLCSP technology is still not fully accepted on the large device size that is larger than 5mm × 5mm. It needs to overcome 2nd level reliability issue on both solder joint and drop reliability test. To improve 2nd level reliability, we need to apply the longer stand–off design such as Cu –post and double solder ball instead of single solder ball, and low modulus material on polymer layer under the solder pad for releasing thermal stress which result in the solder joints crack due to CTEs (Coefficient of Thermal Expansion) mismatch between organic PCB and WLCSP. In this paper, the double ball structure is introduced as one of them can provide the longer stand off. In addition of improving 2nd level reliability and drop test it may need to apply different solder ball component properties to increase Thermal cycling and drop test. The WLCSP structured a double solder ball showed a better 2nd level reliability result. This paper describes the molding process for double ball process and 2nd level reliability by solder property variation.

Drop impact reliability of edge-bonded lead-free chip scale packages

This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.

Investigation of the Role of Void Formation at the Cu-to-Intermetallic Interface on Aged Drop Test Performance

Chip-scale packages (CSPs) are widely used in portable electronic products. Mechanical drop testing is a critical reliability requirement for these products. With the switch to lead-free solder, new reliability data must be generated. Most drop test reliability data reported for CSPs are for the as-built condition. However, the mechanical shock reliability over the life of the product is equally important. This paper provides a systematic study of surface finish (immersion Sn and immersion Ag) and reflow profile (cool down rate) on the drop test reliability of CSP assemblies. A limited experiment was also performed with organic solderability preservative (OSP)-coated boards. The Sn finish provides an initial Cu-Sn intermetallic layer, while the Ag finish and OSP coating allows the formation of the initial Cu-Sn intermetallic during the reflow cycle. Drop test results for assemblies as-built and as a function of aging at 125 degC are correlated with cross-sectional analysis of the solder joints. The mean number of drops to failure decreases by approximately 80% with aging at 125 degC through 480 h. Voids develop at the Cu-Sn intermetallic-to-Cu interface during high-temperature aging, but the crack path is through the intermetallic layer and does not propagate from void-to-void. Thus, it can be concluded that the voids do not contribute to the decrease in drop test survivability observed in this study

Reliability of lead-free interconnections under consecutive thermal and mechanical loadings

To simulate more realistically the effects of strains and stresses on the reliability of portable electronic products, lead-free test assemblies were thermally cycled (−45°C/+125°C, 15-min. dwell time, 750 cycles) or isothermally annealed (125°C, 500 h) before the standard drop test. The average number of drops to failure increased when the thermal cycling was performed before the drop test (1,500 G deceleration, 0.5 ms half-sine pulse). However, the difference was not statistically significant due to the large dispersion in the number of drops to failure of the assemblies drop tested after the thermal cycling. On the other hand, the average number of drops to failure decreased significantly when the isothermal annealing was carried out before the drop test. The failure analysis revealed four different failure modes: (1) cracking of the reaction layers on either side of the interconnections, (2) cracking of the bulk solder, (3) mixed mode of component-side intermetallic and bulk solder cracking, and (4) voidassisted cracking of the component-side Cu3Sn layer. The assemblies that were not thermally cycled or annealed exhibited only type (1) failure mode. The interconnections that were thermally cycled before the drop test failed by mode (2) or mode (3). The drop test reliability of the thermally cycled interconnections was found to depend on the extent of recrystallization generated during the thermal cycling. This also explains the observed wide dispersion in the number of drops to failure. On the other hand, the test boards that were isothermally annealed before the drop testing failed by mode (4).

Lead-Free Chip Scale Packages: Assembly and Drop Test Reliability

Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.