DRAM Power Research Articles

Estimating Overhead Performance of Supervised Machine Learning Algorithms for Intrusion Detection

Estimating the energy and memory consumption of machine learning(ML) models for intrusion detection ensures efficient allocation of system resources. This study investigates the impact of supervised ML algorithms on the energy and memory consumption of intrusion detection systems. Experiments are conducted with seven ML algorithms and a proposed ensemble model, utilizing two intrusion detection datasets. Pearson correlation coefficient(PCC) and Spearman correlation coefficient are employed for the selection of optimum features. Regarding energy consumption, the findings reveal that the PCC with the UNSW-NB15 dataset uses the least amount of DRAM and CPU power. For ML methods, SVM utilizes the highest energy for both feature selection methods and datasets. Concerning memory consumption, the results show that decision tree uses the most current memory with PCC on the UNSW-NB15. The proposed ensemble model demonstrates the highest performance. These findings offer practical guidelines to ML experts when choosing the optimum model with the most efficient utilization of energy and memory.

Advances in parallel and distributed computing and its applications

Advances in parallel and distributed computing and its applications

Thermal design power and vectorized instructions behavior

AbstractVectorized instructions were introduced to improve the performance of applications. However, they come at the cost of an increase in the power consumption. As a consequence, processors are designed to limit their frequency when such instructions are used in order to respect the thermal design power limit. In this paper, we study and compare the impact of thermal design power and Simple Instruction Multiple Data (SIMD) instructions on performance, power and energy consumption of processors and memory. The study is performed on three different architectures providing different characteristics and four applications with different profiles (including one application with different phases, each phase having a different profile). The study shows that, because of processor frequency, performance and power consumption are strongly related to thermal design power. It also shows that AVX512 has unexpected behavior regarding processor power consumption, while DRAM power consumption is impacted by SIMD instructions because of the generated memory throughput. Finally, this paper tackles the impact of turboboost which shows equivalent to better performance for all the studied cases while not always decreasing energy consumption.

Revealing DRAM Operating GuardBands Through Workload-Aware Error Predictive Modeling

Improving the energy efficiency of DRAMs becomes very challenging due to the growing demand for storage capacity and failures induced by the manufacturing process. To protect against failures, vendors adopt conservative margins in the refresh period and supply voltage. Previously, it was shown that these margins are too pessimistic and will become impractical due to high-power costs, especially in future DRAM technologies. In this article, we present a new technique for automatic scaling the DRAM refresh period under reduced supply voltage that minimizes the probability of failures. The main idea behind the proposed approach is that DRAM error behavior is workload-dependent and can be predicted based on particular program inherent features. We use a Machine Learning (ML) method to build a workload-aware DRAM error behavior model based on the program features which we extract from real workloads during our DRAM error characterization campaign. With such a model, we identify the marginal value of the DRAM refresh period under relaxed voltage for each DRAM module of a server that enable us to reduce the DRAM power. We implement a temperature-driven OS governor which automatically sets the module-specific marginal DRAM parameters discovered by the ML model. Our governor reduces the DRAM power by 24 percent on average while minimizing the probability of failures. Unlike previous studies, our technique: i) does not require intrusive changes to hardware; ii) is implemented on a real server; iii) uses a mechanism that prevents any abnormal DRAM error behavior; and iv) can be easily deployed in data centers.

Hardware Memory Management for Future Mobile Hybrid Memory Systems

The current mobile applications have rapidly growing memory footprints, posing a great challenge for memory system design. Insufficient DRAM main memory will incur frequent data swaps between memory and storage, a process that hurts performance, consumes energy, and deteriorates the write endurance of typical flash storage devices. Alternately, a larger DRAM has higher leakage power and drains the battery faster. Furthermore, DRAM scaling trends make further growth of DRAM in the mobile space prohibitive due to cost. Emerging nonvolatile memory (NVM) has the potential to alleviate these issues due to its higher capacity per cost than DRAM and minimal static power. Recently, a wide spectrum of NVM technologies, including phase-change memories (PCMs), memristor, and 3-D XPoint has emerged. Despite the mentioned advantages, NVM has longer access latency compared to DRAM and NVM writes can incur higher latencies and wear costs. Therefore, the integration of these new memory technologies in the memory hierarchy requires a fundamental rearchitecting of traditional system designs. In this work, we propose a hardware-accelerated memory manager (HMMU) that addresses in a flat address space, with a small partition of the DRAM reserved for subpage block-level management. We design a set of data placement and data migration policies within this memory manager such that we may exploit the advantages of each memory technology. By augmenting the system with this HMMU, we reduce the overall memory latency while also reducing writes to the NVM. The experimental results show that our design achieves a 39% reduction in energy consumption with only a 12% performance degradation versus an all-DRAM baseline that is likely untenable in the future.

Design of Low-Power Non-Binary LDPC Decoder Exploiting DRAM Refresh Rate Over-Scaling

This brief presents a low-power non-binary low density parity-check decoder design exploiting domain specific information for high-throughput wireless video communication applications. The proposed technique can dynamically scale the refresh rate of DRAM according to channel conditions as well as decoding states, hence to greatly reduce the DRAM power as well as the decoder power with lower refresh overhead. Evaluation results show that the proposed technique can achieve significant decoder power saving than conventional techniques.

Exploiting OS-Level Memory Offlining for DRAM Power Management

Power and energy consumed by main memory systems in data-center servers have increased as the DRAM capacity and bandwidth increase. Particularly, background power accounts for a considerable fraction of the total DRAM power consumption; the fraction will increase further in the near future, especially when slowing-down technology scaling forces us to provide necessary DRAM capacity through plugging in more DRAM modules or stacking more DRAM chips in a DRAM package. Although current DRAM architecture supports low power states at rank granularity that turn off some components during idle periods, techniques to exploit memory-level parallelism make the rank-granularity power state become ineffective. Furthermore, the long wake-up latency is one of obstacles to adopting aggressive power management (PM) with deep power-down states. By tackling the limitations, we propose OffDIMM that is a software-assisted DRAM PM collaborating with the OS-level memory onlining/offlining. OffDIMM maps a memory block in the address space of the OS to a subarray group or groups of DRAM, and sets a deep power-down state for the subarray group when offlining the block. Through the dynamic OS-level memory onlining/offlining based on the current memory usage, our experimental results show OffDIMM reduces background power by 24 percent on average without notable performance overheads.

Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server

In this paper, we present the implementation of a heterogeneous-reliability DRAM framework, Shimmer , on a commodity server with a fully fledged OS. Shimmer enables splitting of DRAM into multiple domains with varying reliability and allocation of data depending on their criticality. Compared to existing studies which use simulators, we consider practical restrictions stemming from the real hardware and investigate methods to overcome them. In particular, we reveal that the implementation of the heterogeneous-reliability memory framework requires disabling of the hardware memory interleaving, which results in a significant degradation of the system performance. To overcome the induced performance loss, we develop a software-based interleaving. We evaluate the performance, power and energy of the server using 35 benchmarks across three memory configurations: the baseline configuration; with disabled hardware memory interleaving and Shimmer with software-based memory interleaving. Our results show that Shimmer introduces a minor 6% performance overhead, while reducing the average DRAM power by 19.9% when memory operates under relaxed refresh rate and lowered memory supply voltage. As one of our main contributions we demonstrate that a heterogeneous-reliability framework based on Shimmer can be realized on a commodity server and save 9.1% of the total processor and memory energy.

What Your DRAM Power Models Are Not Telling You

Main memory (DRAM) consumes as much as half of the total system power in a computer today, due to the increasing demand for memory capacity and bandwidth. There is a growing need to understand and analyze DRAM power consumption, which can be used to research new DRAM architectures and systems that consume less power. A major obstacle against such research is the lack of detailed and accurate information on the power consumption behavior of modern DRAM devices. Researchers have long relied on DRAM power models that are predominantly based off of a set of standardized current measurements provided by DRAM vendors, called IDD values. Unfortunately, we find that state-of-the-art DRAM power models are often highly inaccurate, as these models do not reflect the actual power consumed by real DRAM devices. To build an accurate model and provide insights into DRAM power consumption, we perform the first comprehensive experimental characterization of the power consumed by modern real-world DRAM modules. Our extensive characterization of 50 DDR3L DRAM modules from three major vendors yields four key new observations about DRAM power consumption that prior models cannot capture: (1) across all IDD values that we measure, the current consumed by real DRAM modules varies significantly from the current specified by the vendors; (2) DRAM power consumption strongly depends on the data value that is read or written; (3) there is significant structural variation, where the same banks and rows across multiple DRAM modules from the same model consume more power than other banks or rows; and (4) over successive process technology generations, DRAM power consumption has not decreased by as much as vendor specifications have indicated. Because state-of-the-art DRAM power models do not account for any of these four key characteristics, they are highly inaccurate compared to the actual, measured power consumption of 50 real DDR3L modules. Based on our detailed analysis and characterization data, we develop the Variation-Aware model of Memory Power Informed by Real Experiments (VAMPIRE). VAMPIRE is a new, accurate power consumption model for DRAM that takes into account (1) module-to-module and intra-module variations, and (2) power consumption variation due to data value dependency. We show that VAMPIRE has a mean absolute percentage error of only 6.8% compared to actual measured DRAM power. VAMPIRE enables a wide range of studies that were not possible using prior DRAM power models. As an example, we use VAMPIRE to evaluate the energy efficiency of three different encodings that can be used to store data in DRAM. We find that a new power-aware data encoding mechanism can reduce total DRAM energy consumption by an average of 12.2%, across a wide range of applications. We have open-sourced both VAMPIRE and our extensive raw data collected during our experimental characterization.

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( $V_{DD}$ and $V_{DDQ}$ ). The proposed calibration scheme improves system signal integrity by maintaining the targeted output level ( $V_{\mathrm {OH}}$ ) in dynamic voltage–frequency scaling (DVFS) function, where $V_{DD}$ and $V_{DDQ}$ can be independently controlled to save system power. A two-step conversion algorithm alleviates the increase in calibration time, which is caused by an additional on-die termination (ODT) calibration for command/address (CA). The offset of a dynamic comparator in a ZQ calibration engine is averaged by a fraction-referred input switching-then-averaging (FISA) scheme which minimizes the effect of kickback noise. A code-referred periodic ZQ update (CPZU) scheme tracks the voltage and temperature variation during the background mode while minimizing the chance of malfunction by interference of both DRAM internal noise and external power noise. By applying the DVFS function based on the device usage by the user scenario in this design ( $V_{DD} =1.1$ V and $V_{DDQ} = 0.95$ V) at 1.6 Gbps, the read and the write operating power consumption can be saved by 17.7% and 18.2%, respectively, without a dynamic drop in performance. Therefore, the proposed dual-loop two-step ZQ calibration design improves the overall DRAM power efficiency based on the existing LPDDR4 SDRAM architecture without circuit overhead.

Power to peep-all: Inference Attacks by Malicious Batteries on Mobile Devices

Abstract Mobile devices are equipped with increasingly smart batteries designed to provide responsiveness and extended lifetime. However, such smart batteries may present a threat to users’ privacy. We demonstrate that the phone’s power trace sampled from the battery at 1KHz holds enough information to recover a variety of sensitive information. We show techniques to infer characters typed on a touchscreen; to accurately recover browsing history in an open-world setup; and to reliably detect incoming calls, and the photo shots including their lighting conditions. Combined with a novel exfiltration technique that establishes a covert channel from the battery to a remote server via a web browser, these attacks turn the malicious battery into a stealthy surveillance device. We deconstruct the attack by analyzing its robustness to sampling rate and execution conditions. To find mitigations we identify the sources of the information leakage exploited by the attack. We discover that the GPU or DRAM power traces alone are sufficient to distinguish between different websites. However, the CPU and power-hungry peripherals such as a touchscreen are the primary sources of fine-grain information leakage. We consider and evaluate possible mitigation mechanisms, highlighting the challenges to defend against the attacks. In summary, our work shows the feasibility of the malicious battery and motivates further research into system and application-level defenses to fully mitigate this emerging threat.

Zebra Refresh: Value Transformation for Zero-Aware DRAM Refresh Reduction

Refresh operations consume growing portions of DRAM power with increasing DRAM capacity. To reduce the power consumption of such refresh operations, this paper proposes a novel value-aware refresh reduction technique exploiting the abundance of zero values in the memory contents. The proposed Zebra refresh architecture transforms the value and mapping of DRAM data to increase consecutive zero values, and skips a refresh operation for a row containing zero values entirely. Zebra converts memory blocks to base and delta values, inspired by a prior compression technique. Once values are converted, bits are transposed to place consecutive zeros matching the refresh granularity. The experimental results show Zebra refresh can reduce DRAM refresh operations by 43 percent on average for a set of benchmark applications.

What Your DRAM Power Models Are Not Telling You

Main memory (DRAM) consumes as much as half of the total system power in a computer today, due to the increasing demand for memory capacity and bandwidth. There is a growing need to understand and analyze DRAM power consumption, which can be used to research new DRAM architectures and systems that consume less power. A major obstacle against such research is the lack of detailed and accurate information on the power consumption behavior of modern DRAM devices. Researchers have long relied on DRAM power models that are predominantly based off of a set of standardized current measurements provided by DRAM vendors, called IDD values. Unfortunately, we find that state-of-the-art DRAM power models are often highly inaccurate when compared with the real power consumed by DRAM. This is because existing DRAM power models (1) are based off of the worst-case power consumption of devices, as vendor specifications list the current consumed by the most power-hungry device sold; (2) do not capture variations in DRAM power consumption due to different data value patterns; and (3) do not account for any variation across different devices or within a device.

Adaptive prediction resolution video coding for reduced DRAM bandwidth

We present a novel approach to video coding that can dramatically reduce decoder DRAM bandwidth requirements while incurring a minimal reduction in compression efficiency, and which may yield an increase in compression efficiency under certain circumstances. Our approach is based on the principle that areas of video pictures where there is high motion are typically captured with significant blur along the direction of motion. This blur permits the judicious use of reduced resolution reference pictures for prediction without significantly reducing prediction quality. Our approach makes it feasible to limit worst-case DRAM bandwidth through the use of reasonably sized on-chip caches for pixel data, which can lead to provably compliant real-time behavior. The reductions in DRAM bandwidth can be expected to yield commensurate reductions in DRAM power dissipation, and consequently improvements in battery life for mobile devices. Although we concentrate our analysis on decoders, our approach can yield even greater advantages for encoders, which require additional bandwidth for motion estimation. We show that the compression efficiency of our encoder can approach that of a standard reference encoder on natural video sequences, but that it may fall short by a modest amount on pathological synthetic sequences.

D-PUF

Physically Unclonable Functions (PUFs) have proved to be an effective and low-cost measure against counterfeiting by providing device authentication and secure key storage services. Memory-based PUF implementations are an attractive option due to the ubiquitous nature of memory in electronic devices and the requirement of minimal (or no) additional circuitry. Dynamic Random Access Memory-- (DRAM) based PUFs are particularly advantageous due to their large address space and multiple controllable parameters during response generation. However, prior works on DRAM PUFs use a static response-generation mechanism making them vulnerable to security attacks. Further, they result in slow device authentication, are not applicable to commercial off-the-shelf devices, or require DRAM power cycling prior to authentication. In this article, we propose D-PUF, an intrinsically reconfigurable DRAM PUF based on the idea of DRAM refresh pausing. A key feature of the proposed DRAM PUF is reconfigurability , that is, by varying the DRAM refresh-pause interval, the challenge-response behavior of the PUF can be altered, making it robust to various attacks. The article is broadly divided into two parts. In the first part, we demonstrate the use of D-PUF in performing device authentication through a secure, low-overhead methodology. In the second part, we show the generation of true random numbers using D-PUF. The design is implemented and validated using an Altera Stratix IV GX FPGA-based Terasic TR4-230 development board and several off-the-shelf 1GB DDR3 DRAM modules. Our experimental results demonstrate a 4.3×-6.4× reduction in authentication time compared to prior work. Using controlled temperature and accelerated aging tests, we also demonstrate the robustness of our authentication mechanism to temperature variations and aging effects. Finally, the ability of the design to generate random numbers is verified using the NIST Statistical Test Suite.

The Reach Profiler (REAPER)

Modern DRAM-based systems suffer from significant energy and latency penalties due to conservative DRAM refresh standards. Volatile DRAM cells can retain information across a wide distribution of times ranging from milliseconds to many minutes, but each cell is currently refreshed every 64ms to account for the extreme tail end of the retention time distribution, leading to a high refresh overhead. Due to poor DRAM technology scaling, this problem is expected to get worse in future device generations. Hence, the current approach of refreshing all cells with the worst-case refresh rate must be replaced with a more intelligent design. Many prior works propose reducing the refresh overhead by extending the default refresh interval to a higher value, which we refer to as the target refresh interval, across parts or all of a DRAM chip. These proposals handle the small set of failing cells that cannot retain data throughout the entire extended refresh interval via retention failure mitigation mechanisms (e.g., error correcting codes or bit-repair mechanisms). This set of failing cells is discovered via retention failure profiling, which is currently a brute-force process that writes a set of known data to DRAM, disables refresh and waits for the duration of the target refresh interval, and then checks for retention failures across the DRAM chip. We show that this brute-force approach is too slow and is detrimental to system execution, especially with frequent online profiling. This paper presents reach profiling, a new methodology for retention failure profiling based on the key observation that an overwhelming majority of failing DRAM cells at a target refresh interval fail more reliably at both longer refresh intervals and higher temperatures. Using 368 state-of-the-art LPDDR4 DRAM chips from three major vendors, we conduct a thorough experimental characterization of the complex set of tradeoffs inherent in the profiling process. We identify three key metrics to guide design choices for retention failure profiling and mitigation mechanisms: coverage, false positive rate, and runtime. We propose reach profiling, a new retention failure profiling mechanism whose key idea is to profile failing cells at a longer refresh interval and/or higher temperature relative to the target conditions in order to maximize failure coverage while minimizing the false positive rate and profiling runtime. We thoroughly explore the tradeoffs associated with reach profiling and show that there is significant room for improvement in DRAM retention failure profiling beyond the brute-force approach. We show with experimental data that on average, by profiling at 250ms above the target refresh interval, our first implementation of reach profiling (called REAPER) can attain greater than 99% coverage of failing DRAM cells with less than a 50% false positive rate while running 2.5x faster than the brute-force approach. In addition, our end-to-end evaluations show that REAPER enables significant system performance improvement and DRAM power reduction, outperforming the brute-force approach and enabling high-performance operation at longer refresh intervals that were previously unreasonable to employ due to the high associated profiling overhead.

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool

In systems ranging from mobile devices to servers, DRAM has a big impact on performance and contributes a significant part of the total consumed power. The performance and power of the system depends on the architecture of the DRAM chip, the design of the memory controller and the access patterns received by the memory controller. Thus, evaluating the impact of DRAM design decisions requires a holistic approach that includes an appropriate model of the DRAM bank, a realistic controller and DRAM power model, and a representative workload, which requires a full system simulator running a complete software stack. In this paper, we introduce DRAMSpec, a high-level DRAM bank/chip modeling tool. Our contribution is to move the DRAM modeling abstraction level from the circuit level to the DRAM bank and by the integration in full system simulators we allow system or processor designers (non-DRAM experts) to tune future DRAM architectures for their target applications. We demonstrate the merits of DRAMSpec by exploring the influence of DRAM row-buffer (page) size and the number of banks on performance and power of a server application (memcached). Our new DRAM design offers a 16% DRAM performance improvement and 13% DRAM energy saving compared to standard comodity DDR3 devices. Additionally, we demonstrate how our tool is able to aid in evaluating novel DRAM architectures, such as the Hybrid Memory Cube (HMC), for which no DRAM datasheets are available. Finally, we highlight the DRAM technology scaling for a specific HMC architecture and we quantify the impact on latency and power.

A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

DRAM Refresh Mechanisms, Penalties, and Trade-Offs

Ever-growing application data footprints demand faster main memory with larger capacity. DRAM has been the technology choice for main memory due to its low latency and high density. However, DRAM cells must be refreshed periodically to preserve their content. Refresh operations negatively affect performance and power. Traditionally, the performance and power overhead of refresh have been insignificant. But as the size and speed of DRAM chips continue to increase, refresh becomes a dominating factor of DRAM performance and power dissipation. In this paper, we conduct a comprehensive study of the issues related to refresh operations in modern DRAMs. Specifically, we describe the difference in refresh operations between modern synchronous DRAM and traditional asynchronous DRAM; the refresh modes and timings; and variations in data retention time. Moreover, we quantify refresh penalties versus device speed, size, and total memory capacity. We also categorize refresh mechanisms based on command granularity, and summarize refresh techniques proposed in research papers. Finally, based on our experiments and observations, we propose guidelines for mitigating DRAM refresh penalties.

Synergy of Dynamic Frequency Scaling and Demotion on DRAM Power Management: Models and Optimizations

Main memory (or DRAM) is one of the most significant components to the computer system's performance and energy consumption. Dynamic frequency scaling (DFS) and DRAM low-power states (Demotion) are two main-stream techniques for DRAM power management. DFS reduces the operation frequency of memory channels and DRAM devices when the memory bandwidth is under-utilized, whereas demotion transits individual memory ranks to low-power states during long idle periods. Despite that there have been fruitful research work for DFS and demotion separately, little attention has been paid to the synergy between these two techniques. To bridge this gap, this paper conducts a comprehensive study on the synergy between DFS and demotion. In particular, we leverage queuing theory to develop analytical models for the energy consumption and performance of DRAM systems with DFS and demotion. These models provide valuable insights into the synergy between DFS and demotion. We further attempt to minimize the energy consumption by considering both DFS and demotion while keeping a pre-defined performance penalty budget. To reduce the optimization complexity, we develop simple yet effective heuristics to search near-optimum DFS-demotion configurations. We experimentally compare our design with other state-of-the-art DRAM energy saving policies using detailed simulations of a large set of workloads. Experimental results show the accuracy of our analytical models and the effectiveness of our optimizations.