DRAM Operation Research Articles

Overhang Saddle Fin Sidewall Structure for Highly Reliable DRAM Operation

Overhang Saddle Fin Sidewall Structure for Highly Reliable DRAM Operation

Silicon Wafer CMP Slurry Using a Hydrolysis Reaction Accelerator with an Amine Functional Group Remarkably Enhances Polishing Rate.

Recently, as an alternative solution for overcoming the scaling-down limitations of logic devices with design length of less than 3 nm and enhancing DRAM operation performance, 3D heterogeneous packaging technology has been intensively researched, essentially requiring Si wafer polishing at a very high Si polishing rate (500 nm/min) by accelerating the degree of the hydrolysis reaction (i.e., Si-O-H) on the polished Si wafer surface during CMP. Unlike conventional hydrolysis reaction accelerators (i.e., sodium hydroxide and potassium hydroxide), a novel hydrolysis reaction accelerator with amine functional groups (i.e., 552.8 nm/min for ethylenediamine) surprisingly presented an Si wafer polishing rate >3 times higher than that of conventional hydrolysis reaction accelerators (177.1 nm/min for sodium hydroxide). This remarkable enhancement of the Si wafer polishing rate for ethylenediamine was principally the result of (i) the increased hydrolysis reaction, (ii) the enhanced degree of adsorption of the CMP slurry on the polished Si wafer surface during CMP, and (iii) the decreased electrostatic repulsive force between colloidal silica abrasives and the Si wafer surface. A higher ethylenediamine concentration in the Si wafer CMP slurry led to a higher extent of hydrolysis reaction and degree of adsorption for the slurry and a lower electrostatic repulsive force; thus, a higher ethylenediamine concentration resulted in a higher Si wafer polishing rate. With the aim of achieving further improvements to the Si wafer polishing rates using Si wafer CMP slurry including ethylenediamine, the Si wafer polishing rate increased remarkably and root-squarely with the increasing ethylenediamine concentration.

Towards Enhanced System Efficiency while Mitigating Row Hammer

In recent years, DRAM-based main memories have become susceptible to the Row Hammer (RH) problem, which causes bits to flip in a row without accessing them directly. Frequent activation of a row, called an aggressor row , causes its adjacent rows’ ( victim ) bits to flip. The state-of-the-art solution is to refresh the victim rows explicitly to prevent bit flipping. There have been several proposals made to detect RH attacks. These include both probabilistic as well as deterministic counter-based methods. The technique of handling RH attacks, however, remains the same. In this work, we propose an efficient technique for handling the RH problem. We show that the mechanism is agnostic of the detection mechanism. Our RH handling technique omits the necessity of refreshing the victim rows. Instead, we use a small non-volatile Spin-Transfer Torque Magnetic Random Access Memory (STTRAM) that ensures no unnecessary refreshes of the victim rows on the DRAM device and thus allowing more time for normal applications in the same DRAM device. Our model relies on the migration of the aggressor rows. This accounts for removing blocking of the DRAM operations due to the refreshing of victim rows incurred in the previous solution. After extensive evaluation, we found that, compared to the conventional RH mitigation techniques, our model minimizes the blocking time of the memory that is imposed due to explicit refreshing by an average of 80.72% in the worst-case scenario and provides energy savings of about 15.82% on average, across different types of RH-based workloads. A lookup table is necessary to pinpoint the location of a particular row, which, when combined with the STTMRAM, limits the storage overhead to 0.39% of a 2 GB DRAM. Our proposed model prevents repeated refreshing of the same victim rows in different refreshing windows on the DRAM device and leads to an efficient RH handling technique.

Design of Processing-“Inside”-Memory Optimized for DRAM Behaviors

The computing domain of today’s computer systems is moving very fast from arithmetic to data processing as data volumes grow exponentially. As a result, processing-in-memory (PIM) studies have been actively conducted to support the data processing in or near memory devices to address the limited bandwidth and high power consumption due to data movement between CPU/GPU and memory. However, most PIM studies so far have been conducted in a way that the processing units are designed only as an accelerator on the base die of 3D-stacked DRAM, not involved inside memory while not servicing the standard DRAM requests during the PIM execution. Therefore, in this paper, we show how to design and operate the PIM computing units inside DRAM by effectively coordinating with standard DRAM operations while achieving the full computing performance and minimizing the implementation cost. To make our goals, we extend a standard DRAM state diagram to depict the PIM behaviors in the same way as standard DRAM commands are scheduled and operated on the DRAM devices and exploit several levels of parallelism to overlap memory and computing operations. Also, we present how the entire architecture layers from applications to operating systems, memory controllers, and PIM devices should work together for the effective execution by applying our approaches to our experiment platform. In our HBM2-based experimental platform to include 16-cycle MAC (Multiply-and-Add) units and 8-cycle reducers for a matrix-vector multiplication, we achieved 406% and 35.2% faster performance by the all-bank and the per-bank schedulings, respectively, at ( $1024\times1024$ ) $\times $ ( $1024\times1$ ) 8-bit integer matrix-vector multiplication than the execution of only its operand burst reads assuming the external full DRAM bandwidth. It should be noted that the performance of the PIM on a base die of a 3D-stacked memory cannot be better than that provided by the full bandwidth in any case.

Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity.

In modern systems, DRAM-based main memory is signi?cantly slower than the processor.Consequently, processors spend a long time waiting to access data from main memory, makingthe long main memory access latency one of the most critical bottlenecks to achieving highsystem performance. Unfortunately, the latency of DRAM has remained almost constant inthe past decade. This is mainly because DRAM has been optimized for cost-per-bit, ratherthan access latency. As a result, DRAM latency is not reducing with technology scaling, andcontinues to be an important performance bottleneck in modern and future systems.This dissertation seeks to achieve low latency DRAM-based memory systems at low costin three major directions. The key idea of these three major directions is to enable and ex-ploit latency heterogeneity in DRAM architecture. First, based on the observation that longbitlines in DRAM are one of the dominant sources of DRAM latency, we propose a newDRAM architecture, Tiered-Latency DRAM (TL-DRAM), which divides the long bitline intotwo shorter segments using an isolation transistor, allowing one segment to be accessed withreduced latency. Second, we propose a ?ne-grained DRAM latency reduction mechanism,Adaptive-Latency DRAM, which optimizes DRAM latency for the common operating conditions for individual DRAM module. We observe that DRAM manufacturers incorporate a very large timing margin as a provision against the worst-case operating conditions, whichis accessing the slowest cell across all DRAM products with the worst latency at the highesttemperature, even though such a slowest cell and such an operating condition are rare. Ourmechanism dynamically optimizes DRAM latency to the current operating condition of theaccessed DRAM module, thereby reliably improving system performance. Third, we observethat cells closer to the peripheral logic can be much faster than cells farther from the peripherallogic (a phenomenon we call architectural variation). Based on this observation, we propose anew technique, Architectural-Variation-Aware DRAM (AVA-DRAM), which reduces DRAMlatency at low cost, by pro?ling and identifying only the inherently slower regions in DRAMto dynamically determine the lowest latency DRAM can operate at without causing failures.This dissertation provides a detailed analysis of DRAM latency by using both circuit-levelsimulation with a detailed DRAM model and FPGA-based pro?ling of real DRAM modules.Our latency analysis shows that our low latency DRAM mechanisms enable significant latencyreductions, leading to large improvement in both system performance and energy e?fficiencyacross a variety of workloads in our evaluated systems, while ensuring reliable DRAM operation.

Effect of OFF-state stress on reliability of nMOSFET in SWD circuits of DRAM

In this paper, we investigate the effect of OFF-State stress occurring at nMOSFET in a sub word-line driver (SWD) circuit under the DRAM operating conditions. Through the experimental study, we found that the increase in the number of OFF-carriers by the OFF-State stress caused the significant decrease of ON-current (Ion). During the initial period, the OFF-State stress generated the positive oxide charges (Qox) and the interface traps (Nit), which caused the increase of OFF-current (Ioff) and the decrease of Ion. After the degradations were saturated, both the Ion and Ioff decreased due to the increase in the number of OFF-carriers. Also the OFF-State degradation increased with decreasing source voltage, channel doping concentration, and channel length. Furthermore, the sensitivity of the OFF-State degradation to body bias (Vb) increased with scaling the oxide thickness (Tox). These new observations suggest that the OFF-State degradation for core transistors can impose the significant limitation on the SWD circuit design in DRAM such as scaling of dimension and determination of word-line voltage.

TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering

Computer systems using DRAM are exposed to row-hammering attacks, which can flip data in a DRAM row without directly accessing a row but by frequently activating its adjacent ones. There have been a number of proposals to prevent row-hammering, but they either incur large area/performance overhead or provide probabilistic protection. In this paper, we propose a new row-hammering mitigation mechanism named T ime Wi ndow C ount e r based row refresh (TWiCe) which prevents row-hammering by using a small number of counters without performance overhead. We first make a key observation that the number of rows that can cause flipping their adjacent ones (aggressor candidates) is limited by the maximum values of row activation frequency and DRAM cell retention time. TWiCe exploits this limit to reduce the required number of counter entries by counting only actually activated DRAM rows and periodically invalidating the entries that are not activated frequently enough to be an aggressor. We calculate the maximum number of required counter entries per DRAM bank, with which row-hammering prevention is guaranteed. We further improve energy efficiency by adopting a pseudo-associative cache design to TWiCe. Our analysis shows that TWiCe incurs no performance overhead on normal DRAM operations and less than 0.7 percent area and energy overheads over contemporary DRAM devices.

In-DRAM Data Initialization

Initializing memory with zero data is essential for safe memory management. However, initializing a large memory area slows down the system significantly. The most likely cause for initialization to slow down the system is the limited DRAM initialization method. At present, the only way to initialize DRAM area is to execute multiple WRITE commands. However, the WRITE command slows the initialization because of its small granularity and data bus occupancy. In this brief, we propose an efficient in-DRAM initialization method inspired by the internal structure and operation of DRAM. The proposed method, called row reset, uses a DRAM row buffer to zero out a single DRAM row at a time. Row Reset allows for parallel initialization on multiple DRAM banks without using off-chip data transfer, thus reducing initialization time by up to 63 times. Row reset is a practical approach, because it can be implemented with existing circuitry in DRAM without additional area overhead.

Bank-Group Level Parallelism

DDR4 SDRAM introduced a new hierarchy in DRAM organization: bank-group (BG). The main purpose of BG is to increase I/O bandwidth without growing DRAM-internal bus-width. We, however, found that other benefits can be derived from the new hierarchy. To achieve the benefits, we propose a new DRAM architecture using the BG-hierarchy, leading to a creation of BG-Level Parallelism (BGLP). By exploiting BGLP, the overall parallelism grows in DRAM operations. We also argue that BGLP is a feasible solution in the cost-sensitive DRAM industry because the additional cost is negligible and only cost-insensitive area needs to be modified.

Rank-Level Parallelism in DRAM

DRAM systems are hierarchically organized: Channel-Rank-Bank. A channel is connected to multiple ranks, and each rank has multiple banks. This hierarchical structure facilitates creating parallelisms in DRAM. The current DRAM architecture supports bank-level parallelism; as many rows as banks can be moved simultaneously at bank-level. However, rank-level parallelism is not supported. For this reason, only one column can be accessed at a time, although each rank has its own data bus that can carry a column. Namely, current DRAM operations do not exploit the structural opportunity created by multiple ranks. We, therefore, propose a novel DRAM architecture supporting rank-level parallelism. Thereby, as many columns as ranks can be moved concurrently at rank-level. In this paper, we illustrate the rank-level parallelism and its benefit in DRAM operations.

Understanding Reduced-Voltage Operation in Modern DRAM Devices

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by DRAM standards. Using an FPGA-based testing platform, we perform an experimental study of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by three major DRAM vendors. We find that reducing the supply voltage below a certain point introduces bit errors in the data, and we comprehensively characterize the behavior of these errors. We discover that these errors can be avoided by increasing the latency of three major DRAM operations (activation, restoration, and precharge). We perform detailed DRAM circuit simulations to validate and explain our experimental findings. We also characterize the various relationships between reduced supply voltage and error locations, stored data patterns, DRAM temperature, and data retention. Based on our observations, we propose a new DRAM energy reduction mechanism, called Voltron. The key idea of Voltron is to use a performance model to determine by how much we can reduce the supply voltage without introducing errors and without exceeding a user-specified threshold for performance loss. Our evaluations show that Voltron reduces the average DRAM and system energy consumption by 10.5% and 7.3%, respectively, while limiting the average system performance loss to only 1.8%, for a variety of memory-intensive quad-core workloads. We also show that Voltron significantly outperforms prior dynamic voltage and frequency scaling mechanisms for DRAM.

Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing ( ${L}_ {\text {gap}})$ between the gates, and an underlap region ( ${L}_{\text {un}})$ between drain and back gate reduces state “0” degradation, which along with optimal biases, results in an improved Retention Time (RT) at 85 °C. The systematic design optimization increases RT from ~80 to ~300 ms with the use of ${L}_{\text {gap}}$ at 85 °C, which can be further improved to ~600 ms with the introduction of ${L}_{\text {un}}$ . The careful investigation shows the back gate scaled down to 25 nm with a front gate region of 100 nm, and operation even at elevated temperatures (125 °C). The insights into DG TFET DRAM operation in terms of individual as well as total lengths highlights the RT enhancement by a factor of 3 with constant total length (200 nm) and an improved scalability with total length scaled down to 160 nm. This paper provides new opportunities to realize TFET-based DRAM with improved RT, scalability, and high temperature operation.

Refresh-Aware Write Recovery Memory Controller

Current computer systems require large memory capacities to manage the tremendous volume of datasets. A DRAM cell consists of a transistor and a capacitor, and their size has a direct impact on DRAM density. While technology scaling can provide higher density, this benefit comes at the expense of low drivability, due to the increase in series resistance of the smaller transistor, which slows the process of restoring the charge in cells. DRAM operations require recovery processes due to the destructive nature of DRAM cells. Among such operations, the write recovery process has the most difficulty in meeting the timing constraints. In this paper, we explore an intrinsic mechanism in the DRAM write operation, and find a relation between restoration and retention times. Based on our observation, we propose a practical mechanism, Relaxed Refresh with Compensated Write Recovery (RRCW), which efficiently mitigates refresh overheads by providing longer restoration periods. Furthermore, to minimize the penalty of the longer restoration, we also introduce another mechanism, Refresh-Aware Write Recovery (RAWR), which appropriately curtails longer recovery time according to the waiting time until being refreshed. Lastly, we introduce a scheduling policy to efficiently utilize RAWR. Evaluations show that the benefits of our mechanisms increase as memory intensity increases.

Improving DRAM Performance in 3-D ICs via Temperature Aware Refresh

The 3-D integration allows IC designs to stack DRAM directly on the top of execution units, which greatly reduces DRAM access latency and improves memory bandwidth. Unfortunately, the heat generated by the processor unit cannot be effectively dissipated. As a result, DRAM operating temperature is undesirably increased. Due to the fact that 3-D-stacked DRAM operates under a severe thermal condition manifested as escalated hot spots and large temperature gradients, conventional refresh schemes based on the peak temperature lead to high refresh rates, which introduce large performance degradation in 3-D-stacked DRAM. To address this problem, we propose the temperature aware refresh technique for 3-D-stacked DRAM. The goal is to mitigate this performance degradation by adjusting the refresh rates of DRAM banks based on their actual thermal conditions at runtime. As a result, only banks that work in the peak temperature will refresh frequently, while the rest of the banks can be refreshed at a reduced rate. This enables more read and write accesses, which improves the overall memory performance.

DRAF

FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devices in environments with tight cost and power constraints. This is the case for datacenter servers, where a modestly-sized FPGA cannot accommodate the large number of diverse accelerators that datacenter applications need. This paper introduces DRAF, an architecture for bit-level reconfigurable logic that uses DRAM subarrays to implement dense lookup tables. DRAF overlaps DRAM operations like bitline precharge and charge restoration with routing within the reconfigurable routing fabric to minimize the impact of DRAM latency. It also supports multiple configuration contexts that can be used to quickly switch between different accelerators with minimal latency. Overall, DRAF trades off some of the performance of FPGAs for significant gains in area and power. DRAF improves area density by 10x over FPGAs and power consumption by more than 3x, enabling DRAF to satisfy demanding applications within strict power and cost constraints. While accelerators mapped to DRAF are 2-3x slower than those in FPGAs, they still deliver a 13x speedup and an 11x reduction in power consumption over a Xeon core for a wide range of datacenter tasks, including analytics and interactive services like speech recognition.

Understanding Latency Variation in Modern DRAM Chips

Long DRAM latency is a critical performance bottleneck in current systems. DRAM access latency is defined by three fundamental operations that take place within the DRAM cell array: (i) activation of a memory row, which opens the row to perform accesses; (ii) precharge, which prepares the cell array for the next memory access; and (iii) restoration of the row, which restores the values of cells in the row that were destroyed due to activation. There is significant latency variation for each of these operations across the cells of a single DRAM chip due to irregularity in the manufacturing process. As a result, some cells are inherently faster to access, while others are inherently slower. Unfortunately, existing systems do not exploit this variation. The goal of this work is to (i) experimentally characterize and understand the latency variation across cells within a DRAM chip for these three fundamental DRAM operations, and (ii) develop new mechanisms that exploit our understanding of the latency variation to reliably improve performance. To this end, we comprehensively characterize 240 DRAM chips from three major vendors, and make several new observations about latency variation within DRAM. We find that (i) there is large latency variation across the cells for each of the three operations; (ii) variation characteristics exhibit significant spatial locality: slower cells are clustered in certain regions of a DRAM chip; and (iii) the three fundamental operations exhibit different reliability characteristics when the latency of each operation is reduced. Based on our observations, we propose Flexible-LatencY DRAM (FLY-DRAM), a mechanism that exploits latency variation across DRAM cells within a DRAM chip to improve system performance. The key idea of FLY-DRAM is to exploit the spatial locality of slower cells within DRAM, and access the faster DRAM regions with reduced latencies for the fundamental operations. Our evaluations show that FLY-DRAM improves the performance of a wide range of applications by 13.3%, 17.6%, and 19.5%, on average, for each of the three different vendors' real DRAM chips, in a simulated 8-core system. We conclude that the experimental characterization and analysis of latency variation within modern DRAM, provided by this work, can lead to new techniques that improve DRAM and system performance.

Fast Bulk Bitwise AND and OR in DRAM

Bitwise operations are an important component of modern day programming, and are used in a variety of applications such as databases. In this work, we propose a new and simple mechanism to implement bulk bitwise AND and OR operations in DRAM, which is faster and more efficient than existing mechanisms. Our mechanism exploits existing DRAM operation to perform a bitwise AND/OR of two DRAM rows completely within DRAM. The key idea is to simultaneously connect three cells to a bitline before the sense-amplification. By controlling the value of one of the cells, the sense amplifier forces the bitline to the bitwise AND or bitwise OR of the values of the other two cells. Our approach can improve the throughput of bulk bitwise AND/OR operations by $9.7X$ and reduce their energy consumption by $50.5X$ . Since our approach exploits existing DRAM operation as much as possible, it requires negligible changes to DRAM logic. We evaluate our approach using a real-world implementation of a bit-vector based index for databases. Our mechanism improves the performance of commonly-used range queries by 30 percent on average.

Methodology for Cycle-Accurate DRAM Performance Analysis

A new methodology for DRAM performance analysis has been proposed based on accurate characterization of DRAM bus cycles. The proposed methodology allows cycle-accurate performance analysis of arbitrary DRAM traces, obviates the need for functional simulations, allows accurate estimation of DRAM performance maximum, and enables root causing of suboptimal DRAM operation.

Modeling of Dynamic Operation of T-RAM Cells

This paper presents a comprehensive simulation analysis of the dynamic operation of T-RAM cells. The analysis addresses the evolution of cell electrostatics and of carrier concentrations and flows in the device when the gate voltage undergoes a fast low-to-high switch, as required by both read and write operations. The results clarify, first of all, the basic physics making holes in the p-base the physical element allowing information storage in the device. From this starting point, the working principles exploited for DRAM operation of the memory cell are then explained.

Understanding and Analyzing the Impact of Memory Controller's Scheduling Policies on DRAM's Energy and Performance

Abstract In current scenario while designing a computing system it is necessary that detailed emphasis should be laid on two common goals, i.e., increasing performance and decreasing power consumption. As we needto achieve either more performance at same power level or minimum power consumption for same performance level. Main memory of a system is one of the key resources that a program needs to run hence it acts as a major contributor towards both system's performance and power consumption. Main memory's performance depends on the way it accesses its contents. It is memory controller's access scheduler that decides which command to issue in every DRAM clock cycle on the basis of employed memory access scheduling policy. Based on underlying access strategy DRAM operations are scheduled in a way that it reduces DRAM's latency and power consumption by utilizing low power modes. In this paper, we have compared and analysedvarious memory access scheduling algorithms on the basis ofpage hit rate, energy-delay product, total execution time and maximum slowdown time. This analysis contributes to better understand how the performance and energy consumption of DRAM memory system is affected by the underlying memory controller's scheduling policies.