Drain Extended NMOS Research Articles

P-type trench gate based drain-extended N-type MOS design for high unclamped inductive switching reliability

The drain-extended NMOS (DeNMOS) is a low-voltage power MOSFET. It comprises intrinsic parasitic BJT (P-BJT), which can trigger under the influence of lattice heating or avalanche-generated holes. The parasitic bipolar current and self-heating effect (SHE) facilitates the second breakdown phenomena near the drain. Hence, we proposed DeNMOS with a P-type trench gate (PTG) placed between the body and source contact to optimize the P-BJT and SHE at high current conditions using the Sentaurus TCAD simulator tool. The PTG increases hole accumulation within the P-body region to optimize the bipolar effect. Furthermore, the proposed DeNMOS (PTG_DeNMOS) structure incorporates an additional heat dissipation path, improving the thermal stability of the device. It is shown that mitigating the P-BJT enhances the device avalanche ruggedness and unclamped inductive switching (UIS) reliability at high current conditions. The analyzed results show that the proposed PTG_DeNMOS ensures UIS reliability at a peak current density 35% higher than the conventional DeNMOS (C_DeNMOS) without compromising mixed signal performance.

Drain Extended MOS Body Region Engineering for Switching Reliability Under Unclamped Inductive Load Conditions

This work presents physical insights on drain extended NMOS (DeNMOS) transient switching reliability under unclamped inductive load (UIL) conditions. The dependence of UIL switching dynamics on the rate of carrier injection after parasitic bipolar junction transistor (P-BJT) triggering and subsequent space charge modulation (SCM) is demonstrated using a 2D TCAD simulation study. In DeNMOS, reduced body resistance suppresses the P-BJT while increasing the back gate bias delays the SCM. We show that the increased body contact length of the proposed DeNMOS offers the dual benefit of P-BJT mitigation and delayed SCM without degrading the DC electrical performance. Furthermore, it is shown that mitigation of P-BJT and delayed SCM enhance the turn-off reliability against thermal runaway when DeNMOS is subjected to transient switching conditions in the presence of UIL. Finally, we show that when external body resistance and bias are individually applied, they result in limited improvement in switching reliability, whereas body layout engineering could achieve optimum switching reliability. Subsequently, a comparative investigation of the body, drain and drift layout optimization techniques shows the highest enhancement in avalanche ruggedness and robustness against thermal runaway for body contact optimized DeNMOS.

Drain-extended MOS design using High-k dielectric to control off-state BTBT with enhanced switching performance

This work explores the application of high-k dielectric to suppress off-state band-to-band tunneling (BTBT) and enhance the switching performance of conventional Drain-extended NMOS (C_DeNMOS). C_DeNMOS switching performance is limited by extended gate over the drift region, while the high field effects near the gate edge are responsible for BTBT below the gate-to-drain overlap region. We investigate two improved configurations of DeNMOS (1) Planar and (2) Trench structures incorporating a floating plate (FP). In comparison to C_DeNMOS, it is demonstrated that employing high-k dielectric HfO2 with appropriately doped FP in the Planar and Trench structures can efficiently modulate the surface field while also reducing surface charge accumulation. As a result, BTBT is suppressed in Planar and Trench structures when HfO2 is used as dielectric, in addition to improvement in switching delay, reverse recovery behavior, and switching energy performance at higher operating frequencies.

System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure.

Drain Extended Tunnel FET—A Novel Power Transistor for RF and Switching Applications

For the first time, a novel drain-extended tunnel FET (DeTFET) device is disclosed in this paper, while addressing the need for high-voltage/high-power devices for system-on-chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunneling and associated carrier injection. Device’s intrinsic (dc/switching), analog, and RF performance is compared with the state-of-the-art drain-extended nMOS (DeNMOS) device. The proposed device for 11 V breakdown voltage offers $15\times $ better subthreshold slope, $8\times $ lower off-state leakage, $2\times $ higher ON current, and absence of channel length modulation and drain induced barrier lowering, while keeping $2.5\times $ lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain, and better RF characteristics, when compared with the DeNMOS device. Finally, device design guidelines are presented and scalability, without affecting breakdown voltage, of the proposed device is compared with the DeNMOS device.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28nm and 40nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87mA/μm to the highest 5.41mA/μm. Under 40nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83mA/μm to 8.79mA/μm and 29.78mA/μm, respectively.

A Drain-Extended MOS Device With Spreading Filament Under ESD Stress

Based on 3-D TCAD simulations, a ten-times improvement in the ESD performance of drain-extended NMOS device is predicted by incorporating deep p-implant underneath the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> drain region. The proposed modification does not degrade the intrinsic MOS characteristics, thus enabling a self-protection ESD concept. Moreover, a detailed physical insight toward the achieved improvement is given.

An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar

A second-breakdown phenomenon (It2) in a drain-extended n-type metal-oxide-semiconductor (DENMOS) is associated with complex triggering of a parasitic bipolar transistor. Full comprehension of the problem requires 3-D modeling; however, there is even deficiency in the understanding of the phenomenon occurring in the 2-D cross-sectional plane. We present experiments and models to understand the physics of bipolar turn-on and its impact on the onset of space-charge modulation in a DENMOS device. We present a detailed analysis of the current paths involved during the bipolar turn-on. We show that a strong snapback is triggered due to coupling of the parasitic bipolar turn-on in a deeper region of the p-body and avalanche injection at the drain junction. Furthermore, we show that the ballast resistor formed in the drain region due to current crowding of electrons under high-current conditions can be modeled through a simplified 1-D analysis of the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> resistive structure.

On-State Hot Carrier Degradation in Drain-Extended NMOS Transistors

A close analysis of the universality of OFF-state hot carrier degradation (HCI) in drain-extended transistors suggests that on-state HCI degradation should likewise be universal. In this paper, we confirm this hypothesis through an extensive set of experiments on drain-extended n-channel metal-oxide-semiconductor (DeNMOS) transistors and demonstrate that the underlying mechanism for both OFF- and ON-state degradation are essentially identical (even though the drain current differs by several orders of magnitude for the respective stress bias conditions). We show how this universality of ON- and OFF-state hot carrier degradations allows the use of short-term measurements to predict device lifetime under arbitrary operating conditions.

Off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown

Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds.

Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs

The dependence of device structures on latchup immunity in a 0.25-mum high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process