Drain Current Oscillations Research Articles

Compact Model of a Bulk FinFET Quantum Dot Toward Single Chip Integration of Qubits and Control Electronics for Quantum Computing Applications

In this work, we thoroughly investigate the drain current oscillations induced by quantum confinement in short channel bulk FinFETs, while operating in coulomb blockade (CB) regime at cryogenic temperature. Various device geometries and layouts of narrow fin-based FinFETs are analyzed experimentally to comprehend the development of quantum dots (QDs). The results demonstrate that the size of QD in the channel is crucial in defining the sensitivity of confinement-related parameters to modifications in device design. To capture the gate and drain bias dependence associated with drain current oscillations in CB regime, we have proposed analytical equations to augment the existing BSIM-CMG compact model. Model-hardware correlation is also presented for n-and p-type bulk FinFETs with different device geometries. The proposed model marks the initial steps toward developing a unified compact model that accurately captures both: the classical behavior of bulk FinFETs and its QD-based tunneling behavior at cryogenic temperatures.

Simulation investigation of double-heterostructure T-gate HEMT with graded back-barrier engineering for improved RF performance

This article proposes a 70 nm T-gate In0.17Al0.83N/AlN HEMT. The RF and DC characteristics of the proposed structure are investigated using the Silvaco Atlas tool. The proposed device has the graded back-barrier feature, which improves the carrier confinement at the GaN/AlGaN junction by increasing the conduction band discontinuity. The reduction of Al composition in the back-barrier layer led to the lattice’s complete relaxation. The presence of a graded back-barrier diminished the piezoelectric polarization, which significantly reduced the 2DEG concentration of the parasitic channel (1.0 × 1018 cm3) about two times and enhanced the transfer characteristics compared to the Al0.1Ga0.9N back-barrier. Moreover, the surface of the device is also passivated with the SiN layer, source/drain regions are highly doped, and the shape of the gate is taken as a T shape. These features improve the transconductance (740 mS/mm), drain current density (2.5 A/mm), cut-off frequency (295 GHz), and maximum oscillation frequency (323 GHz).

Substrate Effects on the Electrical Properties in GaN-Based High Electron Mobility Transistors

We report the electrical characteristics of GaN-based high electron mobility transistors (HEMTs) operated on various substrates/films. For the detailed investigation and comparison of the electrical properties of GaN-based HEMTs according to the substrates/films, GaN-based HEMTs were processed using 4-inch sapphire substrates and separated from their original substrates through the laser lift-off technique. The separated AlGaN/GaN films including processed GaN-based HEMTs were bonded to AlN substrate or plated with a 100 µm-thick Cu at the back-side of the devices since AlN substrate and Cu film exhibit higher thermal conductivity than the sapphire substrate. Compared to the sapphire substrate, DC and RF properties such as drain current, transconductance, cut-off frequency and maximum oscillation frequency were improved, when GaN-based HEMTs were operated on AlN substrate or Cu film. Our systematic study has revealed that the device property improvement results from the diminishment of the self-heating effect, increase in carrier mobility under the gated region, and amelioration of sheet resistance at the access region. C(V) and pulse-mode stress measurements have confirmed that the back-side processing for the device transfer from sapphire substrate onto AlN substrate or Cu film did not induce the critical defects close to the AlGaN/GaN hetero-interface.

The Two-Dimensional Short-Circuit Detection Protection For SiC MOSFETs in Urban Rail Transit Application

This article is an extension of our research, which was presented at the PCIM Europe conference in Nuremberg 2019. After proving the potential of the two-dimensional (2-D) short circuit detection method for SiC mosfet s in the preceding work Hofstetter et al. , this article presents the use of the protection system in an urban rail transit application. This introduces many challenges. It is shown how to calibrate the detection system when facing the challenge of different Miller plateaus due to temperature and dc-link voltage ranges and charge carrier trapping effects. Additionally, the effects due to parallelization are examined. False detections due to drain current oscillation are prevented with a simple additional circuit, which is used to suppress the oscillation from the detection circuit. This method leads to a minor increase in current until detection in a short circuit type 2 event. All the techniques and circuitry are experimentally verified and validate the 2-D short-circuit protection as a perfect candidate for the use in urban rail transit application.

Investigation of Impact of Passivation Materials on the DC/RF Performances of InP-HEMTs for Terahertz Sensing and Imaging

In this work, the effectiveness of various dielectric passivation materials such as SiO2, Si3N4, Al2O3 and Si3N4/Al2O3 on the DC & RF behaviour of InP-HEMT (High Electron Mobility Transistor) was analyzed using TCAD (Sentaurus) tool. The InP HEMT structure used in this work features a novel T-Gate structure with Pt sinking technology to alleviate short channel effects (SCEs), double-Si-δ-doping technique to improve the 2-dimensional charge density in the quantum well (QW) and n+-doped In0.52Ga0.48As drain-source (D-S) areas to effectively minimize the D/S parasitic resistance (RD and RS). The simulations carried out at 300 K using hydro-dynamic (HD) carrier transport model indicate that 25 nm gate length InP HEMT with Si3N4/Al2O3 composite dielectric passivation layer provides the highest transconductance (2814 mS/mm), drain current (1210 mA/mm), cut-off frequency (688 GHz) and maximum oscillation frequency (1340 GHz) compared with other dielectric passivation materials and this is attributed to the minimization of parasitic capacitances due to the improved surface quality of the device. InP HEMTs have been considered as an excellent transistor technology for future high speed wireless/optical communication systems, radiometry and deep space communication systems, sensing and imaging and high speed IC applications.

Analysis of Passivation Techniques in InP HEMTs and Implementation of an Analytical Model of fT Based on the Small Signal Equivalent Circuit.

This paper analyses, the influence of Si₃N₄-PECVD and Al₂O₃-ALD surface passivation on the DC and RF characteristics of InP HEMTs with different gate lengths 0.08 μm, 0.1 μm, 0.12 μm, and 0.15 μm. A significant improvement in maximum drain current IDS, MAX, transconductance gm, MAX and oscillation frequency fmax, MAX is obtained by scaling the thickness of the passivation layers An increase in gm, MAX and fmax, MAX, fT, MAX is observed by reducing parasitic capacitance w.r.t. the decrease in gate length. In addition, an analytical model of fT based on a small-signal equivalent circuit is developed, which consist of extrinsic parameters Rs, Rd, Cgs_ext and Cgd_ext and intrinsic parameters Cgsi, Cgdi, gmi and goi. The carrier transport is improved by increasing gmi, thus the transit time τt , the parasitic charging delay τext and the τpar are reduced by lowering the extrinsic capacitances. An excellent fitting between measured and simulated fT is achieved, which inturn leads a realistic way for further improvement in fT.

Graphene nanoelectromechanical resonators for the detection of modulated terahertz radiation

We propose and analyze a detector of modulated terahertz (THz) radiation based on the graphene field-effect transistor with a mechanically floating gate also made of graphene. The THz component of incoming radiation induces resonant excitation of plasma oscillations in the graphene layers (GLs). The rectified component of the ponderomotive force between the GLs invokes resonant mechanical swinging of the top GL, resulting in drain current oscillations. To estimate the device responsivity, we solve the hydrodynamic equations for the electrons and holes in graphene which govern the plasma-wave response, and the equation describing the graphene membrane oscillations. The combined plasma-mechanical resonance raises the current amplitude by up to four orders of magnitude. The use of graphene for the elastic gate and conductive channel allows the voltage of both resonant frequencies to be tuned within a wide range.

Band structure effect on the electron current oscillation in ultra-scaled GaSb Schottky MOSFET: tight-binding approach

This paper explores band structure effect on the quantum transport of a low-dimensional GaSb Schottky MOSFET (SBFET) for the implementation of III---V transistor with a low series resistance. Precise treatment of the full band structure is employed applying sp 3 d 5 s ∗ tight-binding (TB) formalism. A remarkable distinction between the thickness dependent effective masses extracted from the TB and the bulk values imply that the quantum confinement modifies the device performance. Strong transverse confinement leads to the effective Schottky barrier height increment. Owing to the adequate enhanced Schottky barriers at low drain voltages, a double barrier gate modulated potential well is formed along the channel. The double barrier profile creates a longitudinal quantum confinement and induces drain current oscillation at low temperatures. Significant factors that may affect the current oscillation are thoroughly investigated. Current oscillation is gradually smoothed out as the gate length shrinks down in ultra scaled structure. The results in this paper are paving a way to clarify the feasibility of this device in nanoscale regime.

Steady and Transient Properties of Side-Gated Nano-Transistors

Using a two-dimensional ensemble Monte Carlo (EMC) method, the steady and transient properties of side-gated nanotransistors with single gate and double gate are studied in detail. Simulation results show that the double-gated nanotransistor has more powerful controlling ability on the channel than the single-gated one. The transient processes of the drain current for the two devices are both about 3 ps, which imply that the working speed of the two devices may reach about 0.3 THz. The detail of transient processes for the double-gated nanotransistor is trivial. But for the single-gated nanotransistor, the drain current response shows obviously oscillating during approaching the next steady state. The phenomenon of drain current oscillations is also discussed.

Tight-binding analysis of current oscillation in nanoscale In0.53Ga0.47As Schottky MOSFET

A comprehensive study of band structure effect on the quantum transport of nanoscale In0.53Ga0.47As Schottky MOSFET for the implementation of III–V MOSFET with low source/drain series resistance is presented. Rigorous treatment of the full band structure in ultra-thin body MOSFET is employed using sp3d5s* tight-binding approach. Strong transverse confinement increases the energy of subbands and, indeed, the effective Schottky barrier height. Due to enhanced Schottky barriers and at low drain voltages, a double barrier gate modulated potential well is created along the channel that results in source-to-drain confinement of states. As tunnelling is the main current component in this device, longitudinal confinement induces drain current oscillation at low temperatures. Important factors that may affect current oscillation are demonstrated. Current oscillation that alters the normal performance of the device is investigated in nanowire Schottky MOSFET, as well. Additional quantum confinement in nanowire Schottky MOSFET provides higher effective Schottky barrier height than the double gate structure. Accordingly, the drain current oscillation is more apparent in nanowire Schottky MOSFET than in the double gate device and is gradually smoothed out as the gate length shrinks down in ultra-scaled structure. Effect of diffusive scattering on the quantum transport of the device is investigated, too. What is prominent in our result is that the drain current oscillations degrade as the channel mobility is decreased. The results in this paper are paving a way to elucidate the feasibility of this device in the nanoscale regime.

극저온에서 나노스케일 무접합 p-채널 다중 게이트 FET의 전기적 특성

In this paper, the electrical properties of nanoscale junctionless p-channel MuGFET at cryogenic temperature have been analyzed experimentally. The experiment was performed using a cryogenic probe station which uses the liquid Helium. It has been observed that the drain current oscillation at low drain voltage and cryogenic temperature was more pronounced in junctionless transistor than in accumulation mode transistor. The reason for more marked oscillation is due to the smaller electrical cross section area of the inversion channel which is formed at the center of silicon film in junctionless transistor. It was also observed that the drain current and maximum transconductance were increased as the measurement temperature increased. This is resulted from the increase of hole mobility and the decrease of the threshold voltage as the measurement temperature increases. The drain current oscillation due to the quantum effects can be occurred up to the room temperature when the device size scales down to the nanometer level.

ROOM-TEMPERATURE COULOMB OSCILLATION OF Ni–Nb–Zr–H GLASSY ALLOY

The Ids–Vg characteristics of the aluminum-oxide glassy alloy ( Ni 0.36 Nb 0.24 Zr 0.40)90- H 10 field-effect transistor (GAFET) for gate–drain bias voltage from -50 to +50 μV were measured at room temperature. We observed four kinds of drain current oscillations for gate voltage at two-current plateau regions of -20~-15 and +35~+40 μV. The transistor showed the three-dimensional Coulomb diamond structure. From DC current standards I=ef, we get f=256 GHz for the first peak, being tunneling of one electron.

Room-temperature-operating carbon nanotube single-hole transistors with significantly small gate and tunnel capacitances

Carbon nanotube single-hole transistors operating at room temperature were realized. To obtain large charging energy, a 25-nm-long carbon nanotube channel was formed by shadow evaporation for small gate capacitance and an insulator was inserted between the channel and electrodes for small tunnel capacitances. A significantly small gate capacitance (0.06 aF) and a small tunnel capacitance (0.3 aF) were obtained. The estimated charging energy of a carbon nanotube single quantum dot was 108 meV. Drain current oscillation as a function of gate voltage was clearly observed while typical p-type field effect transistor characteristics were obtained for the device without insulator. These results indicate that the small tunnel capacitance is necessary for the room-temperature-operating carbon nanotube single-charge transistors.

Two-dimensional analysis of the gate–source distance scaling effects in 4H-SiC MESFETs

Two-dimensional dc and small-signal ac analyses of the gate–source scaling effects in SiC-based high-power field-effect transistors have been performed in this paper. The simulation results show that a downscaling of the gate–source distance can improve device performance, enhancing drain current, transconductance and maximum oscillation frequency. This influence is associated with the dynamic characteristic of electrons in SiC MESFETs, which leads to a linear velocity regime in the source access region, even for high drain voltages. The variations of gate-to-source capacitance, gate-to-drain capacitance, cut-off frequency and maximum oscillation frequency with respect to the change in gate–source length have also been studied in detail. The obtained results can be used for a design guideline for the layout of 4H-SiC MESFETs.

Fabrication Technique for Carbon Nanotube Single-Electron Transistors Using Focused Ion Beam

We have proposed a technique for fabricating carbon nanotube single-electron transistors using a focused ion beam (FIB). Wiring to a multiwalled carbon nanotube was formed by the ion-beam-assisted deposition of tungsten. Tunneling barriers were formed in the nanotube by ion beam etching. A drain current oscillation originating from the Coulomb blockade effect was observed at 23 K.

Fabrication of Si single-electron transistors having double SiO2 barriers

We fabricated Si single-electron transistors (SETs) having double SiO2 barriers and a polycrystalline Si (poly-Si) dot. The fabrication method of this device is completely compatible with the complementary metal–oxide–semiconductor technology, and the position of the poly-Si dot is self-aligned between the source and drain regions. The device exhibits drain current (Id) oscillation against gate voltage. From the dot size dependence of the electrical characteristics, the Id oscillation is considered to be due to the Coulomb blockade effect caused by poly-Si grains in the poly-Si dot. The self-alignment of the poly-Si dot in the fabrication process also means that the SET is promising for practical use.

Influence of device geometry on SOI single-hole transistor characteristics

SOI single-hole transistors have been fabricated by intentionally converting a quantum wire to an island connected to source and drain by two narrow constrictions. Two devices with different constriction lengths were investigated. It is found that slight differences in constriction lengths can lead to dramatic differences in device characteristics. For the device with short constrictions, periodic Coulomb oscillations are obtained and persist at temperatures in excess of 100 K. The physical origin of the tunnel barriers of the device has been analyzed experimentally and investigated theoretically based on the self-consistent numerical results of the Schrödinger and Poisson equations. The result indicates that lower ground-state energy for holes in the narrow constrictions serves as a potential barrier responsible for the periodic Coulomb oscillations. For the device with longer constrictions, aperiodic drain current oscillations are observed. The analysis of the experimental results shows that the quantum wire connecting source and drain is converted into at least three islands, probably due to the pattern-dependent oxidation effect. Consequently, the charging energy combined with the quantum confinement energy for the smallest island gives rise to aperiodic drain current oscillations.

Si single-electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process

We studied experimentally and theoretically in detail a Si single-electron tunneling transistor which has a nanoscale floating dot gate stacked on a Coulomb island by a self-aligned process. At 4.2 K, this device exhibits drain current (Id) oscillations due to the Coulomb blockade effect besides the quantized threshold voltage (Vth) shifts with a hysteresis resulting from a single-electron tunneling between the channel and the floating dot gate. The periodicity of the Coulomb oscillation, the voltage separation (ΔVw) between the adjacent two voltages where the Vth shift occurs are consistent with those calculated from the geometrical consideration. The Coulomb oscillation disappeared at room temperature, however, the quantized Vth shifts and hysteresis curves, which are basic operations of single-electron memory, were observed up to room temperature. The fluctuation of electron number in the floating dot was theoretically analyzed at room temperature and we obtained consistent results with the experiments. The high on/off current ratio of the Coulomb oscillation combined with the quantized Vth shifts suggests that it might be possible to produce a memory with ultralow power consumption.

Silicon single-electron quantum-dot transistor switch operating at room temperature

We fabricated a silicon single-electron quantum-dot transistor, which showed drain current oscillations at room temperature. These oscillations are attributed to electron tunneling through a single silicon quantum dot inside a narrow wire channel. Analysis of its current–voltage characteristic indicates that the energy level separation is about 110 meV and the silicon dot diameter is about 12 nm.

Si single electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process

We fabricated a Si single electron tunneling transistor which has a nanoscale floating dot gate stacked on a Coulomb island by a self-aligned process. This device exhibits drain current (Id) oscillations due to the Coulomb blockade effect and quantized threshold voltage (Vth) shifts resulting from a single electron tunneling from the channel to the floating dot gate. The high on/off current ratio of the Id oscillation combined with the quantized Vth shifts leads to the possibility of developing ultralow power consumption memory.