Double Precision Division Research Articles

Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division

Floating point division is a core arithmetic widely used in scientific and engineering applications. This paper proposed an architecture for double precision floating point division. This architecture is designed for dual-mode functionality, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. The architecture is based on the series expansion multiplicative methodology of mantissa computation. For this, a novel dual-mode Radix-4 Modified Booth multiplier is designed, which is used iteratively in the architecture of dual-mode mantissa computation. Other key components of floating point division flow (such as leading-one-detection, left/right dynamic shifters, rounding, etc.) are also re-designed for the dual-mode operation. The proposed dual-mode architecture is synthesized using UMC <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">90 nm</i> technology ASIC implementation. Two versions of proposed architecture are presented, one with single stage multiplier and another with two stage multiplier. Compared to a standalone double precision division architecture, the proposed dual-mode architecture requires 17% to 19% extra hardware resources, with 3% to 5% period overhead. In comparison to prior art on this, the proposed architecture out-performs them in terms of required area, time-period and throughput.

Multiplicative Division Employing Independent Factors

We introduce a division procedure where a normalized quotient approximation is derived as a product of four independent closed form factors. Specific derivations of the method for IEEE-754 standard binary single and double precision division are developed in detail. Theoretical error bounds are derived to prove correctness for obtaining properly rounded single precision quotients by rounding the product of these four factors. The proofs include exhaustive verification for the single precision extremal cases. For double precision quotient approximations, the error bounds verify suitable accuracy so that further determination of the remainder sign is sufficient to obtain precisely rounded double precision quotients. Selected experimental results are provided to illustrate the double precision level quotient approximations. A prescaling process is introduced to reduce the table size requirements for these double precision approximations to less than 5-Kbytes.

Approaches to performance increasing of extended Euclidean algorithm for double precision division on single precision large integers

Public key cryptography has significant processing and spatial complexity. In this regard, relevant scientific and technical challenge is to improve the performance of such transformations. In this paper proposed approaches of large integer’s division operation with double precision on single precision based on the Extended Euclidean Algorithm. These approaches include handling non-zero machine words in the most frequently used operations; using an semi-exact comparison of large integer, without for-word comparison; knowledge of the of Bézout equation parameters changing. These approaches are implemented in the modified algorithm, which has been software implemented. In experiments were compared numbers with double binary size dividend and single binary size divider with ratios for various filled and total binary length. Modified algorithm showed higher performance in 1.5-3 times, with dividend and divisor increasing binary length.

Design of a fast radix-4 SRT divider and its VLSI implementation

The design of a fast divider is an important issue in high-speed computing. The paper presents a fast radix-4 SRT division architecture. Instead of finding the correct quotient digit, an estimated quotient digit is first speculated. The speculated quotient digit is used to simultaneously compute the two possible partial remainders for the next step while the quotient digit is being corrected. Thus, this two-step process does not influence the overall speed. Since the decision-making circuits can be implemented with simple gate structures, the proposed divider offers fast speed operation. Based on the physical layout, the circuit takes 247ns for a double precision division (56 bits for fraction part), where the 2μm CMOS technology in MAGIC is employed and simulated.