Poly Double Metal Research Articles

Extracción de parámetros eléctricos de inversores CMOS de compuerta flotante

This work provides an accurate methodology for extracting the floating-gate gain factor g, of CMOS floating-gate inverters with a clock-driven switch for accessing temporarilly to the floating-gate. With the methodology proposed in this paper, the g factor and other parasiticcapacitances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This parameter plays animportant role in modern analog and mixed-signal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMI-ABN process with 1.2mm design rules, were compared. The extracted parameters can be incorporated into floating-gate PS pice macromodels for obtaining accurate electrical simulation.

DEPFET development at the MPI semiconductor laboratory

The DEPFET device concept offers unique properties that make it useful for applications in X-ray astronomy and particle physics as well as in other fields. They form the basis for two major projects of the MPI Semiconductor Laboratory. This survey reviews device concepts, potential, technology and properties of devices produced at the laboratory. A self-aligning double poly double metal technology has been developed and already the first prototype production run has delivered devices with excellent properties (for example, a noise of ENC=2.2 electrons at room temperature). Another new technology allows the production of very thin (50 μm) detectors.

Titanium Nitride Membrane Application to Extended Gate Field Effect Transistor pH Sensor Using VLSI Technology

A new process for the fabrication of the extended gate field effect transistor (EGFET) together with complementary metal oxide semiconductor (CMOS) circuits on the same chip is reported. The sensing membrane of the EGFET is titanium nitride (TiN) conducting material and it is fabricated using the r.f. sputtering method. The chips are fabricated using the standard submicron 0.5 µm double poly double metal (DPDM) N-well CMOS IC process. No extra mask is used in the post-process. An instrument amplifier circuit is described that provides an output voltage dependent on the threshold-voltage variations in the sensing membrane. According to the experimental results, the high linear sensitivity approaches 57 mV/pH. The hysteresis voltage is 0.5 mV per cycle of buffer solutions of pH7→pH4→pH7→pH10→pH7. This structure is also insensitive to light. This EGFET is fabricated using the standard technology and no difficulty is experienced in realizing this multi species device. The EGFET and readout circuits are produced using VLSI technology, achieving reduced area and low cost. This device has the advantages of mass production.

A novel pH sensitive ISFET with on chip temperature sensing using CMOS standard process

A monolithic chip processing method is reported, which includes the ion sensitive field effect transistor (ISFET) of the pH sensor, p–n diode of temperature sensor and readout circuit using 0.5 μm double poly double metal (DPDM) standard CMOS product with UMC IC foundry company. We have designed a planar diffused silicon diode on a n-channel pH sensitive ISFET sensor to act as a temperature sensor for on-chip temperature measurement and compensation. Furthermore, the device integrated the dual sensors and readout circuit has the potential advantages of achieving, both the pH and temperature value display, with this process, ISFET’s temperature coefficient can be minimized.

CMOS oversampling ΔΣ magnetic-to-digital converters

In this paper, two CMOS oversampling delta-sigma (/spl Delta//spl Sigma/) magnetic-to-digital converters (MDCs) are proposed. The first MDC consists of the magnetic operational amplifier (MOP) and a first-order switched-capacitor (SC) /spl Delta//spl Sigma/ modulator. The second one directly uses the MOP to realize a first-order SC /spl Delta//spl Sigma/ modulator. They can convert the external magnetic field into digital form. Both circuits were fabricated in a 0.5-/spl mu/m CMOS double-poly double-metal (DPDM) process and operated at a 5-V supply voltage and the nominal sampling rate of 2.5 MHz. The dynamic ranges of these converters are at least /spl plusmn/100 mT. The gain errors within /spl plusmn/100 mT are less than 3% and the minimum detectable magnetic field can reach as small as 1 mT. The resolutions are 100 /spl mu/T for both of the two MDCs. The measured sensitivities are 1.327 mv/mT and 0.45 mv/mT for the first and the second MDC, respectively.

A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications

The design and implementation of a fully integrated complementary metal-oxide-semiconductor (CMOS) sixth-order 2.4 Hz low-pass fitter (LPF) for medical applications is presented. For the implementation of large-time constants both linearized operational transconductance amplifiers with reduced transconductance and impedance scalers schemes for grounded capacitors are employed. Experimental results for the filter have shown a dynamic range (DR) of 60 dB, while the harmonic distortion components are below -50 dB. The power consumption for the filter is below 10 /spl mu/W, the power supply is /spl plusmn/1.5 V, and the active area is 1 mm/sup 2/. The filter was fabricated in a double poly double metal 0.8 /spl mu/m CMOS process.

Low-power clock-deskew buffer for high-speed digital circuits

An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6 /spl mu/m single poly double metal CMOS process. The core chip area is 0.9/spl times/0.9 mm/sup 2/. The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3 V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns.

A 25 Ms/s 8-b-10 Ms/s 10-b CMOS data acquisition IC for digital storage oscilloscopes

A data acquisition IC has been developed for digital storage oscilloscopes (DSOs). The entire DSO front-end except an input attenuator was integrated using 1-/spl mu/m double-poly, double-metal (DPDM) CMOS process technology. In the analog-to-digital conversion, a time-interleaved successive approximation architecture effectively enables both 25 Ms/s 8-b and 10 Ms/s 10-b operation. The input signal conditioner consists of a variable gain amplifier (VGA) and a second-order programmable low-pass filter (LPF) using folded-cascode structures with current feedback circuits. The overall gain is externally controllable from 12 dB to 38 dB, and the bandwidth is programmable at 500 kHz, 5 MHz, and 25 MHz. The chip consumes 340 mW at the 25 Ms/s operating condition and less than 8 mW in the power-down mode from a single 5 V supply.

A low-noise low-drift transducer ADC

An analog-to-digital converter (ADC) is described that takes the output from a load-cell transducer directly and performs amplification and signal-conditioning as well as high-resolution conversion. A very low offset drift of 10 nV//spl deg/C is achieved by a chop mode that includes the entire analog signal path. This chop mode adapts easily to dc or ac excitation of the load-cell resistor bridge. An input-referred noise of 31 nV rms is achieved on a 10 mV signal in a 2 Hz bandwidth while employing a purely CMOS switched-capacitor design. The digital low-pass filter, as well as removing chopped offset, has a special mode that enables it to rapidly track step changes in the input from the transducer. Finally, a gain calibration scheme is described that uses precision switched-capacitor attenuation of the 5 V reference voltage to provide an accurate near full-scale calibration voltage, consistent with the low-level input ranges of the converter. The gain drift is 2 ppm//spl deg/C and the power supply rejection (PSR) and common mode rejection (CMR) are 120 dB. The process used is 0.6-/spl mu/m double-poly double-metal (DPDM) CMOS and the die size is 2.73/spl times/4.68 mm.

A 3-V, 2%-mW multibit current-mode ΣΔ DAC with 100 dB dynamic range

The area ratio of analog to digital for mixed-mode chip has been inversely proportional to the process design rule for a given dynamic range objective, in contradiction to the LSI trend. This paper presents a design approach to realize a high degree of size reduction with process design rules for analog circuitry and a signal processing architecture for digital circuitry. A five-level current-mode /spl Sigma//spl Delta/ digital-to-analog converter (DAC) system reveals full scale total harmonic: distortion plus noise (THD+N) of -90 dB and dynamic-range of 100 dB at 3 V (low power of 22 mW). Analog-area down-scaling can be accomplished by this architecture to be 1.09 mm/sup 2/, using 0.6-/spl mu/m double-poly double-metal (DPDM) CMOS. For the digital filter, a pipeline instruction sequence with multiplierless architecture also gives small area of 1.98 mm/sup 2/.