Double Patterning Scheme Research Articles

Plasma Etch Variation Control in Double Patterning Based Metal Hard Mask Open Process

At Cu/low-K interconnection based BEOL etch technology with double patterning scheme, metal hard mask (MHM) etch process is the key step to define final physical structure of Cu line. Gap fill and reliability performance are highly related with MHM pattern CD and profile. During double patterning-based MHM etch process, tri-layers (including organic and inorganic nonmetallic materials) and HM film (e.g. TiN metalloid material) etch processes are involved. Precondition, by-product and etch stop layers are different for each etch flow in double patterning-based MHM open process, which could easily induce final CD variation in first wafer and both trench patterns. First wafer effect with large CD variation in MHM etch process could induce interconnection fail and poor WAT/RE property. In this paper, we investigate double patterning-based MHM etch performance with different etch flow and wafer-less auto clean (WAC)/season process from the viewpoints of CD variation control. Variation control method and mechanism for double patterning-based MHM etch process are also addressed.

Via Bottom Profile Optimization in All-in-One Etch with Double Patterning Scheme

—In advanced CMOS technology node with Cu/low-K interconnection, double patterning scheme with Metal Hard-Mask (MHM) All-In-One (AIO) etch is used to define smaller via and trench. The bottom profile of via is critical for via connectivity and RC delay. Tapered via bottom profile means smaller contact area with lower metal which means larger via contact resistance and degradation of chip interconnect performance. The bottom profile of via may probably become tapered when it enters Etch Stop Layer (ESL) or when the plasma touches lower Cu layer. In this paper, we will explain the reason of tapered via bottom profile and several ways to solve this problem. Keywords—AIO etch; Via bottom taper profile; ESL; Cu exposure; Metal capping layer; Introduction—In current LELE double patterning scheme, the partial via (PV) is firstly formed in 1st mask. Then the second PV is formed in 2nd mask, following by one in-situ ash which will remove PR tri-layer film. Then AIO etch will form via bottom and hard mask defined trench pattern at one etch process synchronously. MHM pattern is also defined by LELE double patterning before PV etch. The process sequence is briefly depicted in Fig.1. In our process, via is self-aligned by MHM for photo lithography reaches its limit on via. After photography critical dimension (CD) is quite large, via CD is shrunk during tri-layer etch process. After shrinking, Via CD is still larger than line CD. Therefore, we use self-aligned via (SAV) to confine via in MHM open area to ensure final VBD and TDDB performance acceptable. In this scheme, we should ensure MHM selectivity during whole etch process to let it not be etched through. Porous ultra-low-k (ULK) is introduced to reduce interconnect RC delay [1]. The etch stop layer (ESL) is introduced to balance different patterns’ loading after PV and trench etch. Then we used a LRM step to open ESL and touch lower Cu layer. However, we found the via bottom profile inside ESL is usually tapered. The tapered via profile into ESL could result in decreased contact area to lower metal Cu which is critical to final RC value. The plasma etch rate in ESL is always relatively slow to make sure the former PV and trench etch step can stop on it. For the practical ULK and ESL film thickness in advanced technology node, the selectivity ULK to ESL should be at least 5 to ensure 80-90% percentage of trench depth is etched by trench etch step, and the following ESL opening step just remove the little trench depth remaining [2]. In final Liner Remove (LRM) step, the etch rate cannot be so fast, meanwhile the etch rate (ER) will be slower after Cu exposure. In fluorocarbon plasma with oxygen, oxygen captures carbon to form C-O bond and control the polymer generation. Such ER change is induced by the reduction of oxygen ion after Cu exposure which will affect the total etch performance to form tapered via bottom profile. In this paper, tradition way to change plasma condition, the change of ESL and the introduction of lower metal capping layer will be used to solve via bottom tapered issue.

Via Bottom Profile Optimization in All-in-One Etch with Double Patterning Scheme

In advanced CMOS technology node with Cu/low-K interconnection, double patterning scheme with Metal Hard-Mask (MHM) All-In-One (AIO) etch is used to define smaller via and trench. The bottom profile of via is critical for via connectivity and RC delay. Tapered via bottom profile means smaller contact area with lower metal which means larger via contact resistance and degradation of chip interconnect performance. The bottom profile of via might probably become tapered when it enters Etch Stop Layer (ESL) or when the plasma touches lower Cu layer. In this paper, we will explain the reason of tapered via bottom profile and several ways to solve this problem.

Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch

The self-aligned double patterning scheme has been developed for subtractive Ge fin patterning targeting critical dimension (CD) <14nm at pitch of 45nm. Compared to the Si self-aligned double patterning route, several modifications have been undertaken in different steps of Ge fin pattering, such as hard mask trimming and main etch. Out of several trimming options, it is the wet trim that has been qualified at the final stage of hard mask CD trimming. It allows meeting CD specifications for all structures and keeping straight lines without wiggling. Finally, the Ge main etch chemistry has been developed, which provides not only a straight fin profile but a flat etching front without depth loading attributed to different density structures.

Implementing registration measurements on photomasks at the Nanometer Comparator

Due to the introduction of double patterning schemes in the production processes of the semiconductor industry and the corresponding stringent specifications of the placement errors of the optical images of mask features (1.2 nm (3σ)) in the lithographic projection process, significant improvements of the registration measurements on photomasks are required. The Nanometer Comparator of the PTB, a one-dimensional vacuum-interference length comparator, has already demonstrated measurement reproducibility at this level on line scales and linear encoders, and therefore this comparator should also be applied for placement metrology on photomasks. Because a photomask is a relatively thin plate which is supported almost at its ends, the bending influence is much larger than for line scales and precautions had to be taken to reduce the influence of the sample support on the measurements results. A new sample mount was built, which exhibits mechanical alignment aids. In addition the position deviations caused by the mask bending were corrected by means of finite element calculations. Measurements performed with the Nanometer Comparator on a high-quality mask showed a maximum deviation of measured feature positions from the common mean of below 0.5 nm and a reproducibility of 0.2 nm. These results suggest that the use of a one-dimensional calibration of mask measuring machines allows us to perform traceable registration measurements with sufficient accuracy.

Dielectric Reliability of 50 nm Half Pitch Structures in Aurora® LK

The dielectric reliability of Aurora® LK (k = 3.0) material has been evaluated on a 50 nm half pitch test structure. These were fabricated using a double patterning scheme and TiN metal hard mask. The introduction of a suitable post-etch residue removal step and close-coupled processing between Cu electroplating and chemical mechanical polishing were found to be key for achieving high yield. Median time-dependent dielectric lifetime of 10 years is reached at an electrical field of 1.4 MV/cm, comparable to earlier reported results with SiO2 as dielectric. The reliability performance is found to be significantly layout dependent with corners being weak points due to local field enhancement.

Double-Patterning Technique Using Plasma Treatment of Photoresist

The double-patterning process was investigated for line-and-space (L/S) patterns of 65 nm half pitch [k1=0.286, 0.85-numerical aperture (NA) ArF dry system] by plasma treatment of photoresist (PR). The sequence of this patterning is exposure–plasma treatment–exposure–etching. Si thin-film passivation and HBr plasma treatment (HPT) were applied, and Si thin-film passivation is preferred to HPT in terms of intermixing prevention and etch selectivity. For planarization of the topographic surface, a thick bottom PR was coated on the pattern after the first exposure. Si thin-film passivation and the thick bottom PR enabled the second exposure to be separated from the first exposure. After the etching process was completed down to the nitride hardmask material, the L/S patterns of 65 nm half pitch were achieved at the full-chip level by virtue of the Si thin-film passivation and thick bottom PR. In the meantime, considering the layout characteristic and process flexibility, layout decomposition and the optical proximity correction (OPC) process were performed. Even though the 65 nm half pitch is defined to be such that k1=0.286, it is believed that this double patterning scheme we suggested can be applied at the minimum pitch over the theoretical limit below 0.25. Consequently, it is expected that the double-patterning technique (DPT) process will have an important role in the extremely low k1 lithography beyond the 32 nm node.