Double Gate Junctionless Field Effect Transistor Research Articles

An analytical 2-D model of triple metal double gate graded channel junctionless MOSFET with hetero-dielectric gate oxide stack

In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO2 and HfO2 is derived. The model illustrates higher drive current and better performance against hazardous SCEs and HCEs in below 30 nm regime. Parabolic approximation method is used here to construct channel potentials and electric fields by solving 2-D Poisson's equation with applicable boundary conditions. The basic central and surface potentials as well as central and surface electric fields are being illustrated, Threshold voltage, DIBL, sub-threshold swing (SS) and a compact current model have also been deduced. These parameters clearly show the benefits of proposed graded-channel triple-metal double-gate structure with hetero-dielectric gate oxide stack. The device has reliability in low power applications because of its better Ion and Ioff control. Finally, the analytical model is validated with self-consistent numerical calculations to illustrate better performance of among available junctionless devices.

A Highly Scalable Junctionless FET Leaky Integrate-and-Fire Neuron for Spiking Neural Networks

In this article, a highly scalable and CMOS compatible double-gate junctionless field-effect transistor (DG-JLFET)-based leaky integrate-and-fire (LIF) neuron is presented for the sub-20 nm gate length which is the smallest reported until now. Using well-calibrated 2-D TCAD simulations, we demonstrated that DG-JLFET LIF is able to mimic biological neuronal behavior. The DG-JLFET LIF neuron shows a low threshold voltage ( -0.31 V) for firing a spike and requires 1.14 pJ of energy per spike which is ~ 32× less than partially depleted silicon-on-insulator (PD-SOI) MOSFET LIF neuron. The proposed neuron needs only 0.4 V of supply voltage that is ~ 7×, 7.5×, 5×, and 2× lower as compared to its counterpart PD-SOI MOSFET, FinFET, L-shaped bipolar impact ionization MOS (LBIMOS), and Si NIPIN Diode-based LIF neurons, respectively. In addition, at a gate length of 10 nm the DG-JLFET LIF requires 0.07 pJ of energy per spike, which is ~ 500×, ~ 642×, and ~ 86× lower than that of the PD-SOI MOSFET, single MOSFET and Biristor based LIF neurons, respectively. Moreover, the DG-JLFET LIF neuron shows spiking frequency in the range of megahertz, which is ~5 orders high compared to the biological neuron. The absence of metallurgical junctions in DG-JLFET eases the fabrication complexity and cuts down the thermal budget requirement.

Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.

Impact of non‐uniformly doped double‐gate junctionless transistor on the performance of 6T‐SRAM bitcell

This work substantiates the impact of Gaussian doping on the electrical performance of double gate junctionless field-effect transistor (DG-JLFET). To get a better understanding of the influence of non-uniform doping, the device is compared with uniform-doped DG-JLFET with various concentrations. The device is later used to demonstrate its usability in six-transistor static random access memory (6T SRAM) bitcell by studying the performance metrics, i.e. stability noise margin and write delay. A comparison of performance metrics is also given with uniformly doped DG-JLFET-based-6T SRAM. Improvement in static noise margin was observed with Gaussian doping without compromising with write access time.

A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects

In this paper, a unified analytical model for the drain current of a symmetric Double-Gate Junctionless Field-Effect Transistor (DG-JLFET) is presented. The operation of the device has been classified into four modes: subthreshold, semi-depleted, accumulation, and hybrid; with the main focus of this work being on the accumulation mode, which has not been dealt with in detail so far in the literature. A physics-based model, using a simplified one-dimensional approach, has been developed for this mode, and it has been successfully integrated with the model for the hybrid mode. It also includes the effect of carrier mobility degradation due to the transverse electric field, which was hitherto missing in the earlier models reported in the literature. The piece-wise models have been unified using suitable interpolation functions. In addition, the model includes two most important short-channel effects pertaining to DG-JLFETs, namely the Drain Induced Barrier Lowering (DIBL) and the Subthreshold Swing (SS) degradation. The model is completely analytical, and is thus computationally highly efficient. The results of our model have shown an excellent match with those obtained from TCAD simulations for both long- and short-channel devices, as well as with the experimental data reported in the literature.

Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors

This paper reports a 2D analytical model for the subthreshold current and subthreshold swing (SS) of ion-implanted Double-Gate Junctionless Field Effect Transistors (DG-JLFETs) with a vertical Gaussian-like doping profile. The effects of gate length, straggle parameter, oxide thickness, channel thickness, and peak doping concentration on subthreshold current and subthreshold swing have been demonstrated. The model results are validated with the simulation data obtained by 2-D TCAD ATLASTM device simulator. Finally, the performance of a CMOS inverter using the DG-JLFET device has been investigated through ATLASTM TCAD mixed mode circuit simulations.

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

In this paper, we have developed a pseudo two-dimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless field-effect transistor. We have incorporated the effects of depletion into the source and drain regions to model the surface potential for all three operating modes: (a) full depletion, (b) partial depletion, and (c) near flatband. The effects of the device parameters such as oxide thickness, silicon thickness, and impurity concentration on the surface potential is demonstrated through the model. The model is further extended to derive an expression for the threshold voltage which predicts the expected change with respect to variation in the device parameters. The accuracy of the proposed model is verified against 2-D numerical simulations.

Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect

We investigate the quantum-mechanical effects on the electrical properties of the double-gate junction-less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation.

Generalized Charge-Based Model of Double-Gate Junctionless FETs, Including Inversion

In this brief, we have developed a charge-based model for the symmetric double-gate junctionless (JL) field effect transistor (FET) that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a former model and aims at giving a unified description of JL FETs beyond the domain of operation for which they have been designed. In addition, to its interest for providing technology design rules, the new model is able to explain the unexpected increase in the gate capacitance when biasing the device in deep depletion as well as the theoretical limit for the OFF-current in deep depletion.

A compact model of subthreshold characteristics for short channel double-gate junctionless field effect transistors

A compact subthreshold characteristics model for short channel fully-depleted double-gate (DG) junctionless field effect transistors (JL FETs) which is based on an approximated solution of 2 dimensional Poisson’s equation has been proposed. The derivation details are introduced and the model’s accuracy has been verified by comparison with both previous models and the TCAD simulations’ results which proves that the subthreshold characteristics such as channel potential distribution, subthrethold drain-to-source current, subthreshold slope, drain-induced-barrier-lowering and threshold voltage can be accurately predicted by our proposed compact model.

Simulation study on short channel double-gate junctionless field-effect transistors

We study the characteristics of short channel double-gate (DG) junctionless (JL) FETs by device simulation. Output I–V characteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed. Distributions of electron concentration, electric field and potential in the body channel region are also analyzed. Comparisons with conventional inversion-mode (IM) FETs, which can demonstrate the advantages of JL FETs, have also been performed.