Double-Gate High Electron Mobility Transistors Research Articles

TCAD‐enabled machine learning framework for DC and RF performance evaluation of InGaAs sub‐channel DG‐HEMTs

AbstractThis research presents a machine learning (ML)‐based model that determines the DC and RF characteristics of InGaAs sub‐channel double gate high electron mobility transistors (DG‐HEMTs) to optimize the device structure. We employ technology computer‐aided design (TCAD) simulations to analyze the DC and RF performance of InGaAs sub‐channel DG‐HEMTs, generating a range of datasets by varying the material composition, layer width, and thickness of different layers in the device structure. We then train and optimize support vector regression (SVR) models using 5‐fold cross‐validation, varying the kernel function and degree parameters, and achieve better performance with the radial basis function (RBF) kernel. The simulated results indicate that the ML model predicts physical parameters more effectively than experimental analysis, offering a compact modeling solution that requires fewer computing resources than traditional methods.

Y-shaped double-gate high electron mobility transistor for radio frequency applications

Y-shaped double-gate high electron mobility transistor for radio frequency applications

Y-Shaped Double-Gate High Electron Mobility Transistor for Radio Frequency Applications

Y-Shaped Double-Gate High Electron Mobility Transistor for Radio Frequency Applications

Three-dimensional analytical modeling for small-geometry AlInSb/AlSb/InSb double-gate high-electron-mobility transistors (DG-HEMTs)

A simple physics-based three-dimensional (3-D) analytical model for AlInSb/AlSb/InSb double-gate high-electron-mobility transistors (DG-HEMTs) is presented. The model accurately predicts the short-channel effects (SCEs) in the channel region for various device dimensions, viz. channel length and width, by solving the three-dimensional Poisson equation. The effects of the barrier layer (AlInSb) thickness and the high doping concentration on the threshold voltage are also considered. Analytical expressions for the surface potential and threshold voltage are derived, and the analytical results closely match those obtained from Sentaurus technology computer-aided design (TCAD) simulations. The drain current and transconductance of the AlInSb/AlSb/InSb double-gate HEMT device are compared with experimental data obtained for a quantum-well field-effect transistor (QWFET). The proposed AlInSb/AlSb/InSb double-gate HEMT shows excellent properties for use in high-speed and low-power applications.

Analysis of microwave noise in an enhancement-mode dual-quantum-well InAs HEMT

A systematic theoretical study is carried out on the microwave noise performance of an InAs-based dual-quantum-well double-gate high-electron mobility transistor. The proposed dual-quantum-well HEMT shows prominent small-signal analog/radiofrequency (RF) and noise performance. The results for a device with a gate length of 30 nm reveal enhancement-mode operation with a threshold voltage (Vt) of 0.146 V and high transconductance of 4.77 S/mm along with a cutoff frequency (ft) of 810 GHz and maximum oscillation frequency (fmax) of 900 GHz for Vds = 0.5 V with reduced parasitic capacitance (Cgg) of 0.003 pF/mm. The high-frequency noise of this device is estimated from the gate and drain noise spectral densities evaluated by a Green’s function method under varying bias conditions. This device shows a minimum noise figure (NFmin) of 1.62 dB in combination with an equivalent noise resistance of 972 Ω at 810 GHz for Vgs = 0.6 V and Vds = 0.5 V, which is relatively low and suitable for the design of low-noise amplifiers for use in high-frequency applications. This study shows that such an InAs HEMT with a dual-quantum-well structure is highly suitable for use in higher-frequency applications that require low noise.

Sheet‐carrier density and I‐V analysis of In0.7Ga0.3As/InAs/In0.7Ga0.3As/InAs/In0.7Ga0.3As dual channel double gate HEMT for THz applications

AbstractThis paper gives a comprehensive detail about an emerging InAs high electron mobility transistor (HEMT) technology with proper material combination making it suitable for low‐power and high‐frequency applications. Over the decade, various material combinations were adopted to improve the sheet‐carrier density and frequency performances. In this work, we report the performance and optimization of 30‐nm gate length InAs‐based dual channel double gate (DCDG) HEMT for terahertz application. The dual channel is formed in the device due to the combination of five layers (In0.7Ga0.3As/InAs/In0.7Ga0.3As/InAs/In0.7Ga0.3As) and thus provides a significant improvement in drain current and transconductance. Moreover, the gate scaling with optimized gate to drain‐side recess length of gate (Lrd) leads to reduced parasitic (Cgg) and tremendously increases the RF performance metrics fmax and fT. For this device, high drain current of 2.203 mA/μm with peak transconductance of 4.77 mS/μm is observed. Further optimization of Lrd results in peak fT of 810 GHz and fmax of 900 GHz at a drain source voltage Vds = 0.5 V. These parameters empower a feasibility of the device for submillimeter as well as terahertz applications.

Investigation of RF and DC Performance of E-Mode In0.80Ga0.20As/InAs/In0.80Ga0.20as Channel based DG-HEMTs for Future Submillimetre Wave and THz Applications

ABSTRACT In this paper, we systematically investigated the DC and RF behaviour of the novel Enhancement-Mode (E-Mode) Double-Gate High Electron Mobility Transistors (DGHEMTs) using Sentaurus-TCAD software. The scalability of the novel DGHEMT is also studied by analysing the short channel effects. The attractive features of the proposed DGHEMT are intrinsic In0.80Ga0.20As/InAs/In0.80Ga0.20As channel, dual silicon delta doping sheets and platinum (Pt) buried gate technology. The proposed DGHEMT with Lg = 20 nm exhibits a gm_max of 3970 mS/mm and IDS_max of 1650 mA/mm at VGS = 0.6 V and VDS = 0.8 V. The proposed DGHEMT exhibits a threshold voltage of 20 mV which indicates its E-Mode behaviour. The sub-threshold swing (SS) and DIBL values obtained for Lg = 20 nm DGHEMT at VDS = 0.5 V are 74 mV/dec and 78 mV/V respectively. The Lg = 20 nm proposed E-Mode DGHEMT also exhibit a fT and fmax of 826 and 1615 GHz respectively at VDS = 0.6 V. The computed logic gate delay for the Lg = 20 nm DGHEMT is 31.25 fS with an electron velocity under the gate of 6.4 × 107 cm/S. This excellent RF and DC behaviour of the proposed DGHEMT makes them an excellent choice for future sub-millimetre wave and THz frequency applications.

Impact of Gatelength on the Performance of InGaAs/InAs/InGaAs Composite Channel Dual Material Double Gate-High Electron Mobility Transistor Devices for High-Frequency Applications

Impact of Gatelength on the Performance of InGaAs/InAs/InGaAs Composite Channel Dual Material Double Gate-High Electron Mobility Transistor Devices for High-Frequency Applications

Simulation of InGaAs subchannel DG-HEMTs for analogue/RF applications

ABSTRACTThe paper reports on the influence of a barrier thickness and gate length on the various device parameters of double gate high electron mobility transistors (DG-HEMTs). The DC and RF performance of the device have been studied by varying the barrier thickness from 1 to 5 nm and gate length from 10 to 150 nm, respectively. As the gate length is reduced below 50 nm regime, the barrier thickness plays an important role in device performance. Scaling the gate length leads to higher transconductance and high frequency operations with the expense of poor short channel effects. The authors claim that the 30-nm gate length, mole fractions tuned In0.53Ga0.47As/In0.7Ga0.3As/In0.53Ga0.47As subchannel DG-HEMT with optimised device structure of 2 nm In0.48Al0.52As barrier layer show a peak gm of 3.09 mS/µm, VT of 0.29 V, ION/IOFF ratio of 2.24 × 105, subthreshold slope ~73 mV/decade and drain induced barrier lowering ~68 mV/V with fT and fmax of 776 and 905 GHz at Vds = 0.5 V is achieved. These superior performances are achieved by using double-gate architecture with reduced gate to channel distance.

Modeling the back gate effects of AlGaN/GaN HEMTs

This letter reports the design and simulation of novel AlGaN/GaN double-gate high electron mobility transistors (DG HEMTs) featuring enhanced back gate-control of the two dimensional electron gas in AlGaN/GaN heterostructures. A comparison study was carried out to reveal the difference between the performance of the AlGaN/GaN DG HEMTs and single-gate devices. The results show that the DG GaN-HEMTs can potentially offer a higher transconductance gain and better immunity of the short channel effects of drain induced barrier lowering and subthreshold swing than traditional single-gate HEMTs.

Monte Carlo Study of the Dynamic Performance of a 100-nm-Gate InAlAs/InGaAs Velocity Modulation Transistor

We report a Monte Carlo study of the dynamic behavior of an InAlAs/InGaAs velocity modulation transistor (VMT) based on the topology of a double-gate high electron mobility transistor (DG HEMT), which is a HEMT with two opposite gates controlling the carrier flow through the conducting channel. In the VMT, the source and drain electrodes are connected by two channels with different mobilities, and electrons are transferred between both by changing the gate voltages in differential mode (DM). As a result, the drain current is modulated while keeping the total carrier density constant, thus, in principle, avoiding capacitance charging/discharging delays. However, the low values taken by the transconductance, as well as the high capacitance between the two gates in DM operation, lead to a deficient dynamic performance.

Fabrication and fundamentals of operation of an InAlAs/InGaAs velocity modulation transistor

We report the design, fabrication, and characterization of an InP-based InAlAs/InGaAs velocity modulation transistor (VMT) based on the double-gate high electron mobility transistor topology. When electrons are transferred between two channels with different mobility, the drain current is modulated while keeping the total carrier density constant. For the fabrication of the transistor, the epitaxial growth has been optimized in order to accomplish the maximum mobility difference between the two active channels. DC characteristics of our VMT have been extracted and an ensemble Monte Carlo simulator is employed to study the microscopic behavior of the fabricated device. The numerical analysis of the carrier density and velocity variation with the gate bias in differential mode demonstrates the actual velocity modulation operation of the fabricated transistors.

Comparison Between the Noise Performance of Double- and Single-Gate InP-Based HEMTs

The noise performance of InAlAs/InGaAs double-gate (DG) and standard high-electron-mobility transistors (HEMTs) is analyzed by means of an ensemble 2-D Monte Carlo simulator. The DG-HEMT is found to have a better noise behavior than the single-gate (SG) device. The results show a moderate decrease of the and noise parameters for the DG HEMT with respect to that of the SG device, since current fluctuations due to electrons injected into the buffer are eliminated. Moreover, the DG HEMT reveals a significantly lower extrinsic minimum noise figure and a higher associated gain , not only due to the better intrinsic performance but also to the lower contact resistances.

Comparison Between the Dynamic Performance of Double- and Single-Gate AlInAs/InGaAs HEMTs

The static and dynamic behavior of InAlAs/InGaAs double-gate high-electron mobility transistors (DG-HEMTs) is studied by means of an ensemble 2-D Monte Carlo simulator. The model allows us to satisfactorily reproduce the experimental performance of this novel device and to go deeply into its physical behavior. A complete comparison between DG and similar standard HEMTs has been performed, and devices with different gate lengths have been analyzed in order to check the attenuation of short-channel effects expected in the DG-structures. We have confirmed that, for very small gate lengths, short-channel effects are less significant in the DG-HEMTs, leading to a better intrinsic dynamic performance. Moreover, the higher values of the transconductance over drain conductance ratio g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , and, especially, the lower gate resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> also provide a significant improvement of the extrinsic f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> .

Fabrication and characterization of 100-nm In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As double-gate HEMTs with two separate gate controls

In this letter, we demonstrate successful operation of 100-nm T-gates double-gate high electron mobility transistors with two separate gate controls (V/sub g1s/ /spl ne/ V/sub g2s/). These devices are fabricated by means of adhesive bonding technique using enzocyclocbutene polymer. The additional gate enables the variation of the threshold voltage V/sub th/ in a wide range from -0.68 to -0.12V while keeping high cutoff frequency f/sub t/ of about 170 GHz and high maximum oscillation frequency f/sub max/ of about 200 GHz. These devices are considered as being very effective for millimeter-wave mixing applications and are promising devices for the fabrication of velocity modulation transistor (VMT) (Sakaki et al., 1982).

InAlAs–InGaAs Double-Gate HEMTs on Transferred Substrate

We report the fabrication and the dc characterization of the first In/sub 0.52/Al/sub 0.48/As-In/sub 0.53/Ga/sub 0.47/As long double-gate (DG) high-electron mobility transistors (HEMTs). These devices have been obtained using a transferred substrate technique. Although the layer structure has not been optimized, a maximum extrinsic transconductance gm of 450 mS/mm is obtained. At the same bias voltage, the drain current I/sub d/ is 120 mA/mm, which gives a large ratio gm/I/sub d/ of 3.8 V/sup -/, indicating the improvement of the charge control efficiency due to the DG structure.