Double Binary Turbo Research Articles

A Novel Combined Double Binary Turbo Coding and Color Shift Keying Technique for Flicker Mitigation in Multi Carrier Visible Light Communications

Although radio frequency (RF) systems have been developed at a level that can operate almost within theoretical limits in terms of spectral efficiency due to increasing demands, the RF spectrum allocated for wireless mobile communication has started to fill up rapidly and become insufficient. Visible light communication (VLC), one of the optical wireless communication systems, stands out as a promising technology that can be an alternative to RF technology in some application areas and can help meet the demands by playing a complementary role in some application areas. However, VLC systems face the flickering problem. In this study, it is proposed to combine the double binary Turbo coding (DBTC) technique with color shift keying (CSK) modulation, which does not have a flickering problem, as a solution to the flicker problem of VLC systems. The proposed combined DBTC-CSK method is tested on optical OFDM systems from multi-carrier wireless communication systems. Monte-Carlo simulations are performed to verify the performance of the proposed DBTC-CSK-OFDM system in terms of bit-error-rate (BER) over AWGN channel, single-path optical LOS channel and multi-path optical channel. According to the simulation results it is observed that, DBTC-CSK-OFDM system has better BER performance than that of RS–CC coded CSK-OFDM and un-coded CSK-OFDM systems, providing 5.5 dB and 14 dB SNR gain at multi-path optical channel environments, respectively.

Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD

A novel multi-ASIP and network-on-chip (NoC) based flexible architecture for parallel iterative demapping with turbo decoding using signal space diversity (TBICM-ID-SSD) is presented in this brief. The proposed heterogeneous multi-ASIP architecture uses multiple instances of two types of application-specific instruction-set processor (ASIP): one dedicated for turbo decoding and the second for demodulation, besides butterfly-topology-based NoCs. This architecture presents novel and outstanding levels of flexibility and scalability in the design of advanced iterative receivers. It supports modulation schemes from BPSK to 256-QAM for any mapping style and supports 8 state single and double binary turbo codes used in 3GPP-LTE, DVB-RCS, and WiMAX. FPGA prototyping results are presented, and the extra hardware cost required to enable turbo demodulation is evaluated.

A Study on Turbo Coded 16-QAM Bit Allocation in Rice Flat Fading Channel

Abstract The study presented in this paper shows that the coding gain between different allocation modalities between turbo encoder and quadrature amplitude modulator with 16 signal points is over 0.6dB in fading environment. The study presents comparatively the performances obtained with the single binary and double binary turbo codes of memory 4 (with 16 states) used in the LTE and DVB standards. It took into consideration the channel with flat fading, non-selective in frequency, of Ricean type for various degrees of strength. Because of the preferential protection offered by the quadrature amplitude modulation, the various modes of binary allocation between turbo encoding and the quadrature amplitude modulation provide very different bit error rates performances. The hierarchies in performance are strongly influenced by the signal per noise ratio at which work is done. The presented results are a guide for choosing the most adequate binary allocation modality between coding and modulation for specific applications.

A low-memory intensive decoding architecture for double-binary convolutional turbo code

Memory accesses take a large part of the power consumption in the iterative decoding of double-binary convolutional turbo code (DB-CTC). To deal with this, a low-memory intensive decoding architecture is proposed for DB-CTC in this paper. The new scheme is based on an improved maximum a posteriori probability algorithm, where instead of storing all of the state metrics, only a part of these state metrics is stored in the state metrics cache (SMC), and the memory size of the SMC is thus reduced by 25%. Owing to a compare-select--recalculate processing (CSRP) module in the proposed decoding architecture, the unstored state metrics are recalculated by simple operations, while maintaining near optimal decoding performance.

LED-ID 시스템을 위한 이중 이진 터보 코딩의 성능

유비쿼터스 시대에 발맞춰 LED를 이용한 WPAN(Wireless Personal Area Network) 기술 개발이 진행 중이다. 그러나 LED를 이용한 가시광 통신은 통신 성능이 저하되는 취약점이 있다. 백열등, 형광등, 태양광선 등과 같은 광잡음으로 인한 정보의 손실을 줄이기 위해 채널 코딩 방식인 이중 이진 터보 코딩을 제안하고자 한다. 본 논문에서는 제안된 시스템의 부호화 방식을 설명하고 시뮬레이션 결과를 분석하여 제안한 이중 이진 터보 코딩을 이용하여 기존의 가시광 통신 시스템의 성능이 향상된 것을 확인할 수 있었다. At the ubiquitous age, applications of Wireless Personal Area Network (WPAN) technology using LEDs are in progress. However, visible light communication using LED have weakness, which deteriorates performance of communication. To reduce information losses, which is caused by optical noise, such as incandescent lamps, fluorescent lamps, sunbeam etc., proposed channel coding scheme, double binary turbo codes. In this paper, encoding scheme of the proposed system is described and simulation results are analyzed. We had expected improved performance by using double binary turbo codes. Finally, performances of the proposed system came up to our expectations.

A Memory Access Decreased Decoding Scheme for Double Binary Convolutional Turbo Code

A Memory Access Decreased Decoding Scheme for Double Binary Convolutional Turbo Code

On the Influence of the Extrinsic Information Scaling Coefficient on the Performance of Single and Double Binary Turbo Codes

On the Influence of the Extrinsic Information Scaling Coefficient on the Performance of Single and Double Binary Turbo Codes

Double Binary Turbo Coded Data Transmission of STBC UWB Systems for U-Healthcare Applications

In this paper, we analyze and simulate performance of space time block coded (STBC) binary pulse amplitude modulation-direct sequence (BPAM-DS) ultra-wideband (UWB) systems with double binary turbo code in indoor environments for various ubiquitous healthcare (u-healthcare) applications. Indoor wireless channel is modeled as a modified Saleh and Valenzuela (SV) model proposed as a UWB indoor channel model by the IEEE 802.15.SG3a in July 2003. In the STBC encoding process, an Alamouti algorithm for real-valued signals is employed because UWB signals have the type of real signal constellation. It is assumed that the transmitter has knowledge about channel state information. From simulation results, it is shown that the STBC scheme does not have an influence on improving bit error probability performance of the BPAM-DS UWB systems. It is also confirmed that the results of this paper can be applicable for u-healthcare applications.

DVB-RCS Next Generation을 위한 Third-dimension Turbo Code 분석

차세대 무선통신에서는 현재 서비스 되고 있는 성능보다 높은 BER(Bit Error Rate)의 성능을 요구한다. 기존의 DVB-RCS(Digital Video Broadcasting - Return Channel via Satellite)에서 사용중인 이진 터보 코드(Double binary Turbo code)는 높은 SNR(에서 오류마루 현상이 발생하여 차세대 무선통신에서 사용하기가 어려움이 있다. 따라서 본 논문에서는 DVB-RCS NG에 적합한 부호화 방식으로 3D-터보 코드(Tthird-dimension Turbo code)의 부복호화기의 구조를 분석하고 성능분석 하였다. 3D-터보 코드는 기존의 DVB-RCS 방식에 rate-1인 post-encoder를 첨가시켜 오류마루 현상을 보완한 부호화기이다. 3D-터보 코드는 post-encoder의 형태, 인터리빙 기법, <TEX>${\lambda}$</TEX>값의 변화에 따라 성능이 달라지므로 본 논문에서는 각 파라메타에 대한 최적의 값을 제시하였다. 전체적으로 3D-터보 코드가 기존의 DVB-RCS 터보 코드에 비해 성능이 우수하고 기존의 문제점인 오류마루 현상을 해결할 수 있음을 알 수 있다. The next generation wireless communication systems are required high BER performance better than present performance. Double binary Turbo code have error floor at high SNR, so it cannot be used in next generation wireless communication system. Therefore, many methods are proposed for overcome error floor at DVB-RCS NG(next generation). In this paper, we analysis structure of third-dimension Turbo code(3D-turbo code). 3D-Turbo code overcomes error flow by additive post-encoder in conventional DVB-RCS Turbo code. Performance of 3D-Turbo code is changed by post-encoder form, interleaving method, value of <TEX>${\lambda}$</TEX>. So we are simulated by those parameter and proposed optimal form. By a result, performance of 3D-Turbo is better than conventional DVB-RCS Turbo code and it overcome error floor of conventional DVB-RCS Turbo code.

High-Speed and Low-Complexity Decoding Architecture for Double Binary Turbo Code

We propose a high-speed and low-complexity architecture for the very large-scale integration (VLSI) implementation of the maximum a posteriori probability (MAP) algorithm suited to the double binary turbo decoder. For this purpose, equation manipulations on the conventional Linear-Log-MAP algorithm and architectural optimization are proposed. It is shown by synthesized simulations that the proposed architecture improves speed, area and power compared with the state-of-the-art Linear-Log-MAP architecture. It is also observed that the proposed architecture shows good overall performance in terms of error correction capability as well as decoder hardware's speed, complexity and throughput.

Iterative Coding for High Speed Power Line Communication Systems

Abstract In this paper, we simulate and analyze performance of iterative coding scheme, double binary turbo code, for high speed power line communication (PLC) systems. PLC system has hostile environment for high speed data transmission, so error correction method is necessary to compensate effects of PLC channel. We employ the PLC model proposed by M. Zimmerman and Middleton Class A interference model, and system performance is evaluated in terms of bit error rate (BER). From the simulation results, we confirm double binary turbo code provides considerable coding gains to PLC system and BER performance is significantly improved as the number of iteration increase. It is also confirmed that BER performance increases as code rate is lager, while it decreases as the code rate is smaller. Key Words : Double binary turbo code, power line communication, Max-log-MAP, OFDM * 광운대학교 전파공학과 * 준회원, 광운대학교 전파공학과 ** 준회원, 전기연구원 *** 정회원, 광운대학교 전파공학과접수일자 2010.10.4, 수정일자 2011.9.2게재확정일자 2011.10.14 Ⅰ. 서 론

Performance of double binary turbo coding for high speed PLC systems

In this paper, performance of double binary turbo coded orthogonal frequency division multiplexing (OFDM) system is analyzed and simulated in power line communications (PLC) channel. In order to make power line channel environments, Bernoulli-Gaussian noise is considered. The performance is evaluated in terms of bit error probability. From the simulation results, it is demonstrated that the double binary turbo coding scheme offers considerable coding gain with reasonable encoding complexity. It is also shown that the system performance can be substantially improved by increasing the number of iterations.

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding

Emerging digital communication applications and the underlying architectures encounter drastically increasing performance and flexibility requirements. In this paper, we present a novel flexible multiprocessor platform for high throughput turbo decoding. The proposed platform enables exploiting all parallelism levels of turbo decoding applications to fulfill performance requirements. In order to fulfill flexibility requirements, the platform is structured around configurable application-specific instruction-set processors (ASIP) combined with an efficient memory and communication interconnect scheme. The designed ASIP has an single instruction multiple data (SIMD) architecture with a specialized and extensible instruction-set and 6-stages pipeline control. The attached memories and communication interfaces enable its integration in multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffled decoding technique introduced in the turbo-decoding field to achieve higher throughput. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for all simple and double binary turbo codes of existing and emerging standards. Results obtained for double binary WiMAX turbo codes demonstrate around 250 Mb/s throughput using 16-ASIP multiprocessor architecture.

차세대 T-DMB 방송의 부가 서비스 제공을 위한 비트 분리 방법 및 Double Binary Turbo 부호 적용 연구

T-DMB(Terrestrial Digital Multimedia Broadcasting) system, is based on the Eureka-147 standard, provides various multimedia data services. However T-DMB system needs upgrades for more various services and better services. Therefore, we proposed advanced T-DMB system using unequal error protection system and hierarchical modulation in this paper while maintaing backward compatibility. And we simulated various bit split methods and double binary turbo code of DVB-RCS standard as method of LP data stream for additional service of advanced T-DMB. As the simulation results, double binary turbo code of proposed advanced T-DMB system have each coding gain of over 2 dB compared to conventional T-DMB.

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding

This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-mum CMOS process, which can support 24.26 Mbps at 200 MHz.

A Hybrid ARQ Using Double Binary Turbo Codes

We propose an incremental redundancy (IR)-hybrid ARQ (HARQ) scheme which uses double binary turbo codes for error correction. The proposed HARQ scheme provides a higher throughput at all E s /N o than the binary turbo IR-HARQ scheme. An extra coding gain is also attained by using the proposed HARQ scheme over turbo codes only.