Double-binary Turbo Decoder Research Articles

High-Speed and Low-Complexity Decoding Architecture for Double Binary Turbo Code

We propose a high-speed and low-complexity architecture for the very large-scale integration (VLSI) implementation of the maximum a posteriori probability (MAP) algorithm suited to the double binary turbo decoder. For this purpose, equation manipulations on the conventional Linear-Log-MAP algorithm and architectural optimization are proposed. It is shown by synthesized simulations that the proposed architecture improves speed, area and power compared with the state-of-the-art Linear-Log-MAP architecture. It is also observed that the proposed architecture shows good overall performance in terms of error correction capability as well as decoder hardware's speed, complexity and throughput.

Memory reduced MAP decoding for double-binary turbo decoder

In this paper, we proposed the branch metric recovery scheme to reduce the memory requirement of MAP decoding for double-binary convolutional turbo code. The proposed technique exploits the fact that huge memory size is required to store the branch metrics in double-binary convolutional turbo decoder. In the proposed method, rather than storing the original branch metrics, the partial terms of the branch metric are stored and the branch metrics are recovered with simple additions. The implementation results based on the proposed technique are presented to show the extremely low overhead compared to the huge memory reduction.

Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes

Nonbinary turbo codes have many advantages over single-binary turbo codes, but their decoder implementations require much more memory, particularly for storing symbolic extrinsic information to be exchanged between two soft-input-soft-output (SISO) decoders. To reduce the memory size required for double-binary turbo decoding, this paper presents a new method to convert symbolic extrinsic information to bit-level information and vice versa. By exchanging bit-level extrinsic information, the number of extrinsic information values to be exchanged in double-binary turbo decoding is reduced to the same amount as that in single-binary turbo decoding. A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method, which reduces the total memory size by 20%.

Performance optimization and parallelization of turbo decoding for software-defined radio

This paper describes the optimization, parallelization, and simulated execution performance of a software double-binary turbo decoder implementation supporting the WiMAX standard suitable for software-defined radio (SDR). Turbo codes offer excellent error-correcting performance, but they introduce significant computational demands in a communication system. In order to enhance execution performance for SDR, software for a turbo decoder based on the maximum a posteriori (MAP) algorithm was first adapted from the open-source Coded Modulation Library. Optimization and parallelization of the adapted software were then pursued and assessed with a multiprocessor version of the SimpleScalar simulator. Simulation results show that serial optimizations of the original adapted stand-alone C decoder software improve performance by more than 200%. The use of special instructions to accelerate important functions provides a further benefit of nearly 40% relative to the new baseline for performance. Exploiting the parallelism available in the MAP algorithm then yields a speedup of 10.8 on 12 processors. Simulation also shows that cache effects do not have a significant impact on parallel execution times.