Double-balanced Gilbert-cell Mixer Research Articles

Design and Analysis of a Reconfigurable Gilbert Mixer for Software-Defined Radios.

A reconfigurable -boosted, image-rejected downconversion mixer is presented in this paper using the SiGe 8 HP technology. The proposed mixer operates within 0.9–13.5 GHz that is suitable for software-defined radio applications. The conversion mixer comprises of resistive biased radio frequency (RF) section, double balanced Gilbert cell mixer core sections divided as per I and Q stages for image-rejection purpose, inductively peaked -boosting section and tunable filter section, respectively. In comparison to previous works in the scientific literature, the design shows enhanced conversion gain (CG), noise figure (NF), and image-rejection ratio (IRR). For the entire band of operation, the mixer attains a good return loss of <−10 dB. Additionally, the design accomplishes an excellent CG of 22 dB, NF of 2.5 dB, and an image-rejection ratio of 30.2 dB at maximum frequency. Finally, a third-order intercept point (IP3) of −3.28 dBm and 1 dB compression point (CP1) of −13 dBm, respectively, shows moderate linearity performance.

Design and Optimization of Double Balanced Gilbert Cell Mixer in 130 nm CMOS Process

An improved design procedure for double balanced Gilbert cell mixer is proposed for specific gain and power requirements at various license exempted frequency ranges for a variety of wireless equipment in India. The down conversion mixer design is aimed to carry out in 130 nm CMOS process. At 2.5 mW d.c power, a conversion gain of over 10 dB and a noise figure under 10 dB is intended at minimum overdrives for transconductance and switching stages of the mixer. Several optimization techniques for enhancement of gain, linearity and noise performances of the designed mixer are presented. An improvement in linearity about 10 dBm is targeted for 1-dB gain compression as well as third order intercept points introducing a unique criterion to integrate and exhaustively explore the enhancement techniques while preserving the gain as well as noise performance of the mixer.

A Compact V-Band Upconversion Mixer With −1.4-dBm OP1dB in SiGe HBT Technology

This letter presents a compact and linear V-band upconverting double-balanced Gilbert cell mixer implemented in a $0.13-\,\mu \text{m}$ SiGe BiCMOS technology. The detailed design procedure for the on-chip transformer baluns is provided, which enables the compact implementation. The mixer occupies an area of $365\,\,\mu \text{m}\,\,\times 400\,\,\mu \text{m}$ with pads and $175\,\,\mu \text{m}\,\,\times 300\,\,\mu \text{m}$ without pads, consuming 52 mW from a 2.5-V power supply. The mixer achieves an OP1dB of −1.4 dBm at 60-GHz radio frequency, intermediate frequency (IF) bandwidth of 0.5–8.5 GHz on both sidebands, a maximum conversion gain of 13.4 dB, and a 3-dB bandwidth of 50 to above 67 GHz. The performance of the proposed mixer outperforms other state-of-the-art V-band mixers in terms of chip area, IF bandwidth, and linearity.

A 3-5 GHz Low Power UWB Mixer Using Tunable Active Inductors

This paper presents the design of a low power up conversion double balanced Gilbert cell mixer using 0.18 µm CMOS technology. The proposed circuit uses a dynamic current bleeding technique made of a single transistor and two active inductors to resonate the tail capacitances at the LO switches so to increase the conversion gain and decrease the noise figure. It also adopts a post distortion cancellation technique made of two auxiliary transistors that linearize the input current and absorb the third order intermodulation distortion which considerably improve the linearity of the circuit. Performed simulations showed a conversion gain of 13.31 dB at the central frequency of the UWB (3-5GHz) third channel, a minimum noise figure of 8.6 dB and an IIP3 that reached 4.2 dBm. The circuit consumes a low power of about 5.2 mW from a 1.8V dc supply voltage and corner simulations showed that the process variations have small effect on the proposed circuit’s performance.

Harmonic Rejection in 2.4 GHz Gilbert Cell Mixer for Terrestrial Microwave Communication systems

Mixer is one of the significant components of the radio frequency transceiver that translate baseband signal into RF and vice versa. In this paper, 2.4 GHz double balanced Gilbert Cell Mixer topology was simulated to study its important properties such as Conversion Gain, Linearity, Noise Figure and Port Isolation. Further, a band pass filter is added in to the design at IF port so as to reject harmonics. The mixer topology is designed and simulated using NMOS 180 nm CMOS technology in Advanced Design Systems. As a result, conversion gain of 8.303 dB, high linearity, high port isolation and Harmonic Rejection Ratio > 80 dB is achieved. General Terms Harmonic rejection in down conversion Gilbert cell Mixer

67–80 GHz double‐balanced Gilbert‐cell mixer in 0.1 μm GaAs pHEMT technology

A 67–80 GHz double-balanced Gilbert-cell mixer fabricated in 0.1 μm gallium arsenide pseudomorphic high-electron-mobility transistor technology is presented. Two Marchand baluns were placed in RF and local oscillator (LO) input ports to convert single-ended signals to differential signals for wideband use. A differential amplifier between the switch and output stages was used to enhance the conversion gain (CG). The mixer demonstrated an average CG of 14.1 ± 2.1 dB at an LO power of 0 dBm from 67 to 80 GHz. The measured intermediate frequency 3 dB bandwidth was 3 GHz and the input 1 dB compression point was −4.8 dBm.

A low power and low noise 60-GHz CMOS receiver front-end with high conversion gain and excellent port-to-port isolation

A 60-GHz receiver front-end using standard 90-nm CMOS technology is reported. The receiver front-end comprises a wideband low-noise amplifier, and a double-balanced Gilbert cell mixer with a current-reused RF single-to-differential converter, an LO marchand balun and a baseband amplifier. The receiver front-end consumes 34.4 mW and achieves LO-RF isolation of 60.7 dB, LO-IF isolation of 45.3 dB and RF-IF isolation of 41.9 dB at RF of 60 GHz and LO of 59.9 GHz. At IF of 0.1 GHz, the receiver front-end achieves maximum conversion gain (CG) of 26.1 dB at RF of 64 GHz and CG of 25.2 dB at RF of 60 GHz. The corresponding 3-dB bandwidth of RF is 7.3 GHz (58.4---65.7 GHz). The measured minimum noise figure was 5.6 dB at 64 GHz, one of the best results ever reported for a 60 GHz CMOS receiver front-end. In addition, the measured input 1-dB compression point and input third-order inter-modulation point are ?33.1 and ?23.3 dBm, respectively, at 60 GHz. These results demonstrate the adopted receiver front-end architecture is very promising for 60 GHz direct-conversion transceiver applications.

A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor

This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using $$0.18\,\upmu \hbox {m}$$ 0.18 μ m CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential active inductor (DAI) circuit and cross-coupled current injection technique within the conventional double-balanced Gilbert cell mixer. A cross-coupled current bleeding circuit is used to inject the current to the switching stage to decrease the flicker noise. Instead of spiral inductor, a DAI with high tunability of the inductor and quality factor is used to tune out the parasitic capacitance effect and decrease the leakage current that has a harmonic component and produce the flicker noise. By tuning the DAI, the flicker noise corner frequency is reduced to 150 Hz. The proposed circuit is simulated with Cadence Spectra and the simulation results shows the NF of 11.2 dB, conversion gain of 23.7 dB and IIP3 of $$-6$$ - 6 dB for an RF frequency of 2.4 GHz. The excellent LO-RF, LO-IF, RF-LO and RF-IF isolations of $$-60, -110, -52$$ - 60 , - 110 , - 52 and $$-64$$ - 64 dB are achieved respectively. The total power consumption is 10.5 mW from a 1.8 V DC power supply.

Flicker noise reduction in RF CMOS mixer using differential active inductor

This article presents a low flicker noise (1/f), double-balanced Gilbert-cell mixer. As the down converted base-band signal is strongly affected by the low-frequency flicker noise, resulting in mixer signal-noise ratio (SNR) degradation, a dynamic current injection technique has been used to reduce the flicker noise corner frequency. Differential active inductor has been used to tune the tail capacitance at the node between the local oscillator (LO) switches and the radio frequency (RF) transconductance stages, resulting in reduction of RF leakage. RF and LO leakage has been minimized by adding an on-chip low-pass filter to the mixer output. The mixer has been designed and fabricated using Taiwan Semiconductor Manufacture Company (TSMC) 0.18-μm 1P6M complementary metal-oxide-semiconductor FET (CMOS) process. The performance of the fully integrated mixer is given. With RF of 2.4 GHz, intermediate frequency of 10 MHz and LO power of −5 dBm, conversion gain of 12 dB, input third order intercept point (IIP3) of −5.5 dBm, and single-side band noise (SSB-NF) figure of 15 dB with flicker noise corner frequency of 300 KHz had been measured. The mixer consumes 19.8 mW from 1.8 V supply. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2553–2556, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26366

Nanoscale CMOS Transceiver Design in the 90–170-GHz Range

This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately + 2 dBm and a phase noise of -90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

High-performance current bleeding CMOS mixer

A high-performance mixer, known as the amplifier-driven double-balanced Gilbert-cell mixer, is proposed and implemented in 0.18 µm RFCMOS technology. A class-A amplifier-based current bleeding source is used to amplify the local oscillator signal and improve transconductance of the transconductor stage. The conversion gain is measured to be 17.5 dB when the LO power is −14 dBm only. The measured noise figure is better than 12.5 dB. The chip area is 1.2×1.3 mm and the power consumption is 12 mA at 1.5 V supply voltage.

A Wideband W-Band Receiver Front-End in 65-nm CMOS

A 75-to-91 GHz receiver front-end, consisting of a three-stage cascode low-noise amplifier (LNA), a double-balanced Gilbert-cell mixer and a differential DC-to-9 GHz IF buffer, is reported in 65-nm general purpose (GP) CMOS technology. The noise and input-impedance matched LNA employs a cascode input stage with shunt-series, transformer feedback. A theoretical and experimental comparison with a conventional inductor-feedback LNA indicates 0.5-1 dB higher gain, 0.3-0.6 dB lower noise figure and better input return loss for the transformer feedback LNA. The receiver has a differential down-conversion gain of 13 dB, an input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of -16.2 dBm, and a double-sideband noise figure of 8.5 to 10 dB at an IF of 1 GHz. Because of the transformer feedback, the input return loss is better than -20 dB from 80 to 92 GHz and remains below -10 dB from 70 GHz beyond 95 GHz. The circuit occupies an area of 460 mum times 500 mum and consumes 89 mW (47 mW in the LNA and mixer) from a 1.5 V supply. An LO-to-RF isolation of 60 dB was measured for LO signals in the 80-to-85 GHz range. Measurements of the mixer breakout, which includes transformers at the RF and LO ports, show a record NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSB</sub> of 8 to 10 dB over the 74-to-91 GHz band. The 50-Omega noise figure of the LNA is 6.4 to 8.4 dB in the 75-to-88.5 GHz range. The LNA can also be employed as a transmitter output stage with a saturated output power of +4 dBm.

165-GHz Transceiver in SiGe Technology

Two D-band transceivers, with and without amplifiers and static frequency divider, transmitting simultaneously in the 80-GHz and 160-GHz bands, are fabricated in SiGe HBT technology. The transceivers feature an 80-GHz quadrature Colpitts oscillator with differential outputs at 160 GHz, a double-balanced Gilbert-cell mixer, 170-GHz amplifiers and broadband 70-GHz to 180-GHz vertically stacked transformers for single-ended to differential conversion. For the transceiver with amplifiers and static frequency divider, which marks the highest level of integration above 100 GHz in silicon, the peak differential down-conversion gain is -3 dB for RF inputs at 165 GHz. The single-ended, 165-GHz transmitter output generates -3.5 dBm, while the 82.5-GHz differential output power is +2.5 dBm. This transceiver occupies 840 mum times 1365 mum, is biased from 3.3 V, and consumes 0.9 W. Two stand-alone 5-stage amplifiers, centered at 140 GHz and 170 GHz, were also fabricated showing 17 dB and 15 dB gain at 140 GHz and 170 GHz, respectively. The saturated output power of the amplifiers is +1 dBm at 130 GHz and 0 dBm at 165 GHz. All circuits were characterized over temperature up to 125degC. These results demonstrate for the first time the feasibility of SiGe BiCMOS technology for circuits in the 100-180-GHz range.

CMOS RF mixer with digitally enhanced IIP2

A new method to enhance the IIP2 of a double-balanced Gilbert cell mixer through digital calibration is presented. The IIP2 calibration method consists of offset voltage cancellation in the switching pairs. The effectiveness of the method has been proven by calibrating a 0.18 mu m CMOS mixer at several combinations of worst-case mismatch conditions and corners. It has been found that the calibrated mixer can achieve its targeted IIP2 specification even at large process, temperature, and power supply variations.