Doped Double Gate Research Articles

Influence of deep level trap charges on the reliability of asymmetric doped double gate JunctionLess transistor (AD-DG-JLT)

A study based on the numerical simulation of Double Gate JunctionLess Transistor DG-JLT has been presented under the influence of Trap Charges (TC) inside the oxide or at the oxide/channel interface using ATLAS TCAD software. These trap charges may be generated due to various effects like aging and exposure to radiation and chemical environment etc. and thus leading to variability in the device behavior. To evaluate the impact of TC, the forward and reverse threshold voltage were calculated by altering the gate voltage from zero to positive and subsequently returning to zero, while employing various gate bias durations. Asymmetric doping has also been employed to study the variability in DG-JLT with TC as compared to Uniformly Doped DG-JLT (UD-DG-JLT). Furthermore, the investigation is expanded to evaluate how the performance of AD-DG-JLT is affected by the Dual Material Gate (DMG) in the presence of generated TC. To explore the robustness of the device, breakdown voltage (BV) has been examined with varying TC and device specifications. The impact of the trap energy level (EC-ET) on the BV of the devices has also been explored. Extensive numerical simulations have also been performed to showcase the results regarding the change in drain current caused by Single Event Upset (SEU).

Impact of Non-Uniform Doping on the Reliability of Double Gate JunctionLess Transistor: A Numerical Investigation

This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10−9 A to 4 × 10−11 A @ V gs = −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10−9 A @ V gs = −1 V for L S = L D = 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 1019 cm−3 but at the cost of significantly high off-state current (2 × 10−9 A @ V gs = 0 V) and tunneling current (2 × 10−8 A @ V gs = −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10−9 A @ V gs = −1 V), moderate lattice temperature (326) and better I on/I off ratio (243 × 108). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect.

Classical and quantum charge density model of nano scale doped DG MOSFETs below onset of strong inversion

Classical and quantum inversion charge density models are derived below threshold for a doped double-gate (DG) MOSFET. Since our charge density model includes a 2D analytical solution of channel potential considering the contribution of both mobile charge and doping concentration terms, the proposed models are also investigated slightly above threshold of the device having different channel lengths and validated by 2D TCAD (Technology Computer Aided Design) simulation. Quantum Confinement Effects are incorporated in quantum model by considering a 1D infinite rectangular well with a perturbation applied. Finally charge models are implemented in suitable drain current equation to study the electrical behavior of the device.

Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET

This paper proposes a novel design of dynamically configurable electrostatic doped double gate carbon nanotube tunnel FET (ED CN-TFET). The proposed device consists of intrinsic carbon nanotube (CN) as channel and electrostatic doping is created using polarity gates. Polarity gate allows dynamic configuration of source/drain region with different bias conditions. As conventional doping techniques are not applicable to CN which makes fabrication costly, proposed device will offer reduced thermal budget and process complexity. 3-D simulations have been performed and results show that proposed device gives promising results over conventional CN-TFET in terms of ION/IOFF ratio and subthreshold swing (SS). Proposed device has been analysed for various device parameters and it has been demonstrated to give better results as compared to conventional CN-TFET.

Virtually doped SiGe tunnel FET for enhanced sensitivity in biosensing applications

In this work, a novel tunnel FET device architecture based on the concept of charge plasma for biosensing applications has been proposed and the sensing performance has been evaluated by comparing it to a conventionally doped double gate (DG) TFET. The use of a low bandgap material in the source region facilitates the increase in On current of TFETs. The device sensitivity is dependent on dielectric constant as well as charge density of biomolecules. Three different sensing metrics, △VTh/VTh, gm/Ids, SIds have been used to evaluate and compare the performance of biosensors. It is observed that the drain current sensitivity (SIds) and threshold voltage sensitivity △VTh/VTh is ∼1.9 times and ∼1.67 times more in CP-TFET than conventional DG-TFET respectively. The biosensor sensitivity is more dependent on the location of biomolecules within the cavity rather than the fill in factor as found by orientation analysis. The sensitivity metric gm/Ids is 28% higher in CP-TFET than conventional TFET when the biomolecules are confined near the source-channel tunneling junction.

A SILICON GERMANIUM GRADED JUNCTIONLESS TRANSISTOR WITH LOW OFF CURRENT

We propose a Ge / Si graded junctionless transistor (JLT) which helps to reduce the band-to-band tunneling current in off-state for highly doped double gate junctionless transistor (DGJLT). In this paper, we show that there is large band-to-band tunneling (BTBT) current in off-state of silicon-channel and germanium-channel DGJLT, which causes increase in the off-state leakage current by several orders. With the help of band-gap engineering, we found that by using Ge / Si graded channel DGJLT off-state band-to-band tunneling current can be reduced. It is also observed that there is large deviation in the off-state leakage current with variation of drain voltage for Si and Ge body DGJLT, which reduces device stability. It is found that in Ge / Si graded DGJLT variation off-state leakage current with drain voltage is controlled. In Si and Ge , DGJLT electrons from the valence band of the channel tunnel to the conduction band of drain leaves holes which causes increased hole concentration in the channel creating parasitic 'BJT'.

Improved modeling of gate leakage currents for fin–shaped field–effect transistors

Recently, we developed a symmetric doped double gate model for MOSFETs, which includes a direct tunneling model for gate current considering its dependence on the voltages applied to the gate and drain electrodes. Since different tunneling mechanisms can dominate the gate and drain/source leakage currents depending on the transistor operation regime, the gate stack dimensions and the insulating materials used as gate dielectric, in this work, we analyze and model specific features of such currents in SOI FinFET devices. We present an analytical model which takes into account three main conduction mechanisms of leakage currents associated with the gate structure and is valid for a wide operation range. An improved model to describe the behavior of direct tunneling is proposed to avoid the use of fitting parameters. It is shown that carriers tunneling assisted by trap states in the dielectric material of the overlap regions should be considered, as it can become predominant in the subthreshold regime. Moreover, a band-to-band tunneling model is included because of its large impact on the drain leakage current. The present improved model for gate leakage currents is validated by experimental results obtained on FinFETs with different dimensions, gate dielectric materials and performed under different bias conditions.

Modeling of subthreshold characteristics for undoped and doped deep nanoscale short channel double-gate MOSFETs

A model of subthreshold characteristics for both undoped and doped double-gate (DG) MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson's equation using variable separation technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thickness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations' results and found very good agreement.

A two-dimensional model for the subthreshold swing of short-channel double-gate metal–oxide–semiconductor field effect transistors with a vertical Gaussian-like doping profile

An analytical two-dimensional (2D) model for the subthreshold swing of the short-channel double-gate (DG) MOSFET with a vertical Gaussian-like doping profile is presented in this paper. The 2D potential function obtained by solving the 2D Poisson’s equation by using the evanescent mode analysis has been used to formulate the subthreshold current. The concept of the effective conduction path effect of uniformly doped DG MOSFETs has been extended to the nonuniformly doped DG MOSFETs to obtain the subthreshold swing variations against doping profile parameters as well as device parameters of the present device. The results of the model show excellent matching with the numerical simulation data obtained by using the commercially available ATLASTM, a two-dimensional device simulator from SILVACO.

A Two-Dimensional Model for the Surface Potential and Subthreshold Current of Doped Double-Gate (DG) MOSFETs with a Vertical Gaussian-Like Doping Profile

An analytical two-dimensional (2D) model for the surface potential distribution and subthreshold current of the Double-Gate (DG) MOSFETs having Gaussian-like doping profile in the vertical direction of the silicon channel has been presented in this paper. The model is based on the solution of the 2D Poisson's equation in the fully depleted channel region using evanescent method. The effect of doping profile parameters on the surface potential has also been presented. The potential distribution function has been utilized to investigate the subthreshold current characteristics of the device. The validity of the proposed model is shown by comparing the analytical results with the simulation data obtained by the 2D device simulator ATLAS™. The proposed model is considered to be a very accurate and compact one since it does not include any fitting parameter.

Analytic Oxide Capacitance Model of Double- and Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors in Linear Region by Considering Inversion-Layer Capacitance

Inversion charge (Qi) and oxide capacitance (Cox') of undoped (or lightly doped) or doped double-gate (DG) and surrounding-gate (SG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with long channel were analytically modeled by considering inversion-layer capacitance (Ci) in linear region. The Qi model of DG and SG MOSFETs was derived with a closed-form as a function of gate bias (VGS), threshold voltage (Vth), and body structure factor (n) using one-dimensional (1D) Poisson's equation considering the mobile carrier. The n which reflects silicon body structure effect is 1 for DG MOSFETs and less than 1 for SG MOSFETs irrespective of channel doping (Nb). From the derived Qi model considering the Ci effect, the Cox' was modeled and applied to the ID–VGS model of undoped or doped DG and SG MOSFETs in linear region. The compact current model using our proposed Cox' predicted more accurately the on-current behavior than that with the oxide capacitance (Cox) in linear region.

Symmetric and Asymmetric Double Gate MOSFET Modeling

An analytical compact model for the asymmetric lightly doped Double Gate (DG) MOSFET is presented. The model is developed using the Lambert Function and a 2-dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the net charge and channel current of the DGMOSFET are derived in section 2. Results for the channel potential and current are compared with 2-D numerical data for a lightly doped DG MOSFET in section 3, showing very good agreement.