Division In GF Research Articles

Computation of Multiplicative Inversion and Division in GF(2<SUP><I>n</I></SUP>) by Self-Assembly of DNA Tiles

Computation of Multiplicative Inversion and Division in GF(2<SUP><I>n</I></SUP>) by Self-Assembly of DNA Tiles

Fast Hardware Algorithm for Division in $ \hbox{GF}(2^{m})$ Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions

We propose a fast hardware algorithm for division in GF(2m) based on the extended Euclid's algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in two iterations of previously reported division algorithms. Since the algorithm performs modular reductions in parallel by changing the order of execution of the operations, a circuit based on this algorithm has almost the same critical path delay as the previously proposed ones. The circuit computes division in m clock cycles, whereas the previously proposed circuits take 2m - 1 or more clock cycles.

New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations

A new bit-parallel systolic multiplier over GF(2m) under the polynomial basis and normal basis is proposed. This new circuit is constructed by m 2 identical cells, each of which consists of one two-input AND gate, one three-input XOR gate and five 1-bit latches. Especially, the proposed architecture is without the basis conversion as compared to the well-known multipliers with the redundant representation. With this proposed multiplier, a parallel-in parallel-out systolic array has also been developed for computing inversion and division over GF(2m). The proposed architectures are well suited to VLSI systems due to their regular interconnection pattern and modular structure.

New systolic architectures for inversion and division in GF(2/sup m/)

We present two systolic architectures for inversion and division in GF(2/sup m/) based on a modified extended Euclidean algorithm. Our architectures are similar to those proposed by others in that they consist of two-dimensional arrays of computing cells and control cells with only local intercell connections and have O(m/sup 2/) area-time product. However, in comparison to similar architectures, both our architectures have critical path delays that are smaller, gate counts that range from being considerably smaller to only slightly larger, and latencies that are identical for inversion but somewhat larger for division. One architecture uses an adder or an (m+l)-bit ring counter inside each control cell, while the other architecture distributes the ring counters into the computing cells, thereby reducing each control cell to just two gates.

A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/)

A low latency architecture to compute the multiplicative inverse and division in a finite field GF (2/sup m/) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cryptography to increase system throughput. This architecture takes advantage of the simplicity to computing powers (2/sup l/) of an element in the Galois Field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit.

New systolic arrays for C+AB/sup 2/, inversion, and division in GF(2/sup m/)

In this paper, we present a new parallel-in parallel-out systolic array with unidirectional data flow for performing the power-sum operation C+AB/sup 2/ in finite fields GF(2/sup m/). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in GF(2/sup m/). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.

Hardware-efficient systolic architecture for inversion and division in GF(2m)

Two parallel-in parallel-out systolic arrays for computing inverses and divisions in finite fields GF(2/sup m/) with the standard basis representation are presented. Both architectures realise a new variant of Euclid's algorithm. One of the proposed arrays involves O(m/sup 2/) area complexity and O(1) time complexity, while the other involves O(m) area complexity and O(m) time complexity. They are highly regular, modular and thus well suited to VLSI implementation. Compared to existing related systolic architectures with the same time complexity, our proposed arrays involve less chip area and smaller latency. It should be noted that, to perform inversion only, both the proposed arrays can be simplified.

Systolic array implementation of Euclid's algorithm for inversion and division in GF(2/sup m/)

This paper presents two new systolic arrays to realize Euclid's algorithm for computing inverses and divisions in finite fields GF(2/sup m/) with the standard basis representation. One of these two schemes is parallel-in parallel-out, and the other is serial-in serial-out. The former employs O(m/sup 2/) area complexity to provide the maximum throughput in the sense of producing one result every clock cycle, while the latter achieves a throughput of one result per m clock cycles using O(m log,m) area complexity. Both of the proposed architectures are highly regular and, thus, well suited to VLSI implementation. As compared to existing related systolic architectures with the same throughput performance, the proposed parallel-in parallel-out scheme reduces the hardware complexity (and, thus, the area-time product) by a factor of O(m) and the proposed serial-in serial-out scheme by a factor of O(m/log/sub 2/m).

VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2/sup m/)

A modified parallel-in-parallel-out linear-systolic power-sum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). On the basis of the linear-systolic power-sum circuits, a VLSI architecture for exponentiation in GF(2/sup m/) is developed. Furthermore, two modified architectures that can be used to compute inverses and divisions over GF(2/sup m/) are proposed. All the architectures are constructed from m-1 linear-systolic power-sum circuits. It should be noted that the presented exponentiator, inverter, and divider are the only such circuits having a throughput of 100%. The latency of the presented pipeline exponentiator, inverter, and divider is m(m-1) clock cycles. The cycle time (i.e., clock period) of the presented architectures is only two logic gate delays plus a short routing delay. For moderate values of m, say m/spl les/10, the circuit complexity of the presented circuits is realizable using presently available VLSI technology. The computation time of near two gate delays and 100% throughput enables the greatest computation speed in finite field arithmetic.

ACE: a VLSI chip for Galois field GF(2/sup m/) based exponentiation

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. These applications often require computing exponentiations in GF(2/sup m/) which is a very computationally intensive operation. The methods proposed in the literature achieve exponentiation by iterative methods using repeated multiplications and the hardware implementations use a number of Galois field multipliers in parallel resulting in expensive hardware. In this paper, we present a new algorithm based on a pattern matching technique for computing exponentiations in GF(2/sup m/), for values of m/spl les/8. A systolic array processor architecture was developed by the authors for performing multiplication and division in GF(2/sup m/) in [13]. A similar strategy is proposed in this paper for achieving exponentiation at the rate of a new result every clock cycle. A prototype VLSI chip Called ACE implementing the proposed architecture for Galois field GF(2/sup 4/) has been designed and verified using CMOS 2 /spl mu/m technology. The chip can yield a computational rate of 40 million exponentiations per second.

SIGMA: a VLSI systolic array implementation of a Galois field GF(2/sup m/) based multiplication and division algorithm

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. A new algorithm based on a pattern matching technique for computing multiplication and division in GF(2/sup m/) is presented. An efficient systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle and the multiplication and division operations can be interleaved. The architecture has been implemented using 2- mu m CMOS technology. The chip yields a computational rate of 33.3 million multiplications/divisions per second.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A systolic architecture for computing inverses and divisions in finite fields GF(2/sup m/)

A new serial-in serial-out systolic array is presented for performing the element inversion in GF(2/sup m/) with the standard basis representation. The architecture is highly regular, modular, nearest neighbor connected, and thus well suited to VLSI implementation, It has a latency of 7m-3 clock cycles and a throughput rate of one result per 2m)-1 clock cycles. This speed performance is much better than those of the previous implementations. Without change in hardware design, the proposed inversion array can be directly used for computing the division in GF(2/sup m/).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Elliptic Curve Scalar Point Multiplication Algorithm Using Radix-4 Booth’s Algorithm

The main back-bone operation in elliptic curve cryptosystems is scalar point multiplication. The most frequently used method implementing the scalar point multiplication, which is performed in the topmost level of GF multiplication and GF division, has been the double-and-add algorithm, which is being recently challenged by NAF (Non-Adjacent Format) algorithm. In this paper, we propose a more efficient and novel approach of a scalar multiplication method than the double-and-add by applying redundant recoding which originates from the radix-4 modified Booth’s algorithm. We call the novel algorithm quad-and-add. After deriving the algorithm, we created a new GF operation, named point quadruple, and verified with calculations of a real-world application to utilize it. Derived numerical expressions were verified using both C programs and HDL (Hardware Description Language). Proposed method of elliptic curve scalar point multiplication can be utilized in many elliptic curve security applications for handling efficient and fast calculations.