Distributed Memory Organization Research Articles

BEST LOOKUP ALGORITHM FOR 100+GBPS IPV6 PACKET FORWARDING

As internet traffic is growing day by day, it is a key requirement to increase more and more IP addresses. IPv4 cannot accommodate this need due to the exhaustion of its 2 32 address. Hence in order to effectively satisfies this increase in demand for IP address new addressing scheme called IPv6 is developed. It has 2 128 addresses so the exhaustion is not possible in near future. To forward IPv4 packet efficient mechanisms are there. But IPv6 is of 128bit length, so the present forwarding techniques is not possible to forward IPv6 packet effectively. In this paper we try to explore currently existing different lookup algorithms (Distributed Memory Organizations, Triec, Recursive Balanced Multi-way range trees and Range tree based IPv6 lookup) and analyze the best lookup algorithm for 100+ Gbps IPv6 packet forwarding by performing a comparative survey.

Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations

Multiprocessor system-on-chip (MPSoCs) have attracted significant attention since they are recognized as a scalable paradigm to interconnect and organize a high number of cores. Current multicore embedded systems exhibit increased levels of dynamic behavior, leading to unexpected memory footprint variations unknown at design time. Dynamic memory management (DMM) is a promising solution for such types of dynamic systems. Although some efficient dynamic memory managers have been proposed for conventional bus-based MPSoC platforms, there are no DMM solutions regarding the constraints and the opportunities delivered by the physical distribution of multiple memory nodes of the platform. In this work, we address the problem of providing customized microcoded DMM on MPSoC platforms with distributed memory organization. Customization is enabled at application- and platform-level. Results show that customized microcoded DMM can serve approximately 7× more allocation requests compared to pure distributed memory platforms and perform 25% faster than the corresponding high-level implementation in C language.

Deriving Array Distributions by Optimization Techniques

The paper presents a new method to derive data distributions for parallel computers with distributed memory organization by a mathematical optimization technique. Prerequisites for this approach are a parameterized data distribution and a rigorous performance prediction technique that allows us to derive runtime formulas containing the parameters of the data distribution. A mathematical optimization technique can then be used to determine the parameters in such a way that the total runtime is minimized, thus also minimizing the communication overhead and the load imbalance penalty. The method is demonstrated by using it to determine a data distribution for the LU decomposition of a matrix.

Low-power data transfer and storage exploration for H.263 video decoder system

We describe a power exploration methodology for data-dominated applications using a H.263 video decoding demonstrator application. The starting point for our exploration is a C specification of the video decoder, available in the public domain from Telenor Research. We have transformed the data-transfer scheme in the specification, and have optimized the distributed memory organization. This results in a memory architecture with significantly reduced power consumption. For the worst case mode using predicted (P) frames, memory power consumption is reduced by a factor of 7 when compared to the reference design. For the worst case mode using predicted and bi-directional (PB) frames, memory power consumption is reduced by a factor of 9. To achieve these results, we make use of our formalized high-level memory management methodology, partly supported in our ATOMIUM environment.

Deriving structured parallel implementations for numerical methods

The numerical solution of differential equations is an important problem in the natural sciences and engineering. But the computational effort to find a solution with the desired accuracy is usually quite large. This suggests the use of powerful parallel machines which often use a distributed memory organization. In this article, we present a parallel programming methodology to derive structured parallel implementations of numerical methods that exhibit two levels of potential parallelism, a coarse-grain method parallelism and a medium grain parallelism on data or systems. The derivation process is subdivided into three stages: The first stage identifies the potential for parallelism in the numerical method, the second stage fixes the implementation decisions for a parallel program and the third stage derives the parallel implementation for a specific parallel machine. The derivation process is supported by a group-SPMD computational model that allows the prediction of runtimes for a specific parallel machine. This enables the programmer to test different alternatives and to implement only the most promising one. We give several examples for the derivation of parallel implementations and of the performance prediction. Experiments on an Intel iPSC/860 confirm the accuracy of the runtime predictions. The parallel programming methodology separates the software issues from the architectural details, enables the design of well-structured, reusable and portable software and supplies a formal basis for automatic support.