Distortion Optimization Process Research Articles

Towards an FPGA-Based HEVC Encoder: A Low-Complexity Rate Distortion Scheme for AMVP

Advanced motion vector prediction (AMVP) is a new technique adopted in the latest high efficiency video coding (HEVC) standard. AMVP block predicts an initial motion vector of the current block from a given set of candidates by means of rate distortion (RD) optimization process. Due to the large number of different-sized blocks, simplification of RD optimization process in AMVP block is highly appreciated. Therefore, we present a new RD optimization technique for AMVP block in HEVC encoder. The proposed RD calculation approach finds the best AMVP candidate by processing less number of feature pixels per every block. Experimental results show notable speedup in terms of AMVP processing time with tolerable quality degradation (PSNR) and bitrate requirement. The proposed RD calculation technique reduces the RD computational complexity of the AMVP block by 87.5% as maximum (i.e. 1.7% of the whole encoder complexity). This improvement is accompanied with a modest average PSNR loss of 0.10 dB and an increase by 2.4% in terms of bitrate. On the other hand, we present an FPGA-based architecture for AMVP unit in HEVC encoder. The proposed architecture was prototyped, simulated and synthesized on Xilinx Virtex-7 XC7VX550T FPGA. At 188 MHz clock frequency, the proposed architecture processes 8 K (7680 \(\times \) 4320) YCrCb resolution at 60 fps while utilizing less than 1% of the FPGA resources.

An early split and skip algorithm for fast intra CU selection in HEVC

The rapid development and increase of multimedia applications, as well as the demand for higher video-quality services at restricted resources such as storage capacity, transmission bandwidth and power consumption, has brought the urgent need for more efficient video compression techniques. The new video coding standard high efficiency video coding (HEVC) has a significant superiority over its predecessor advanced video coding (AVC). HEVC is reported to halve the bit rate with the same visual quality, or a better quality with the same bit rate when compared with AVC. Beside other improvements, HEVC significantly gets its power from the use of dynamic hierarchical quad-tree structure by partitioning the frames into smaller regions called coding units (CU), by means of a rate---distortion optimization process. However, this improvement yields to a dramatic increase of high computational complexity and increased encoding time, which primarily restricts its adaptation in real-time applications. In this paper, we proposed an early CU determination algorithm for fast encoder realization to reduce the encoding time which is the most important part of the standard standing for development. The experimental results show that the proposed algorithm has approximately 45 % encoding time saving with a 4.6 % bit-rate increment, on average.

Two stage fast mode decision algorithm for intra prediction in HEVC

High efficiency video coding (HEVC) standard, introduced by the joint collaborative team on video coding (JCT-VC), is the newest international standard for video compression. This standard provides more compression and better video quality, compared with the previous standards such as H.264/AVC. The higher compression efficiency in HEVC is achieved at the cost of increasing the computational load. Intra prediction unit is among the high computational stages in the HEVC encoder. There are proposed 35 intra prediction modes in HEVC, to improve the compression efficiency. To reduce the computational load of intra prediction, HEVC uses a preprocessing step, called Rough Mode Decision (RMD). A number of best prediction modes are selected by the RMD stage and then, using Rate Distortion Optimization (RDO) process, the encoder selects the best prediction mode among them. In this paper a two stage algorithm is proposed for fast intra mode decision in HEVC encoder, in the first stage of our proposed algorithm the number of the tested modes in RMD is reduced from 35 to 19. In the second stage, the number of the tested modes in the RDO process is reduced as well. In order to evaluate the performance of the proposed method two encoding profiles, main and main10 were used in the experiments. Experimental results indicate that the proposed method achieves 14.4 and 7.2 % reduction in the encoding time compared with the HEVC reference software in all intra-main and all intra-main10 configurations, respectively. Meanwhile, it imposes minimum reduction in the coding efficiency among the compared methods.