Display Buffer Research Articles

ДОСЛІДЖЕННЯ ФЕРМЕНТНОГО ПРЕПАРАТУ ТРАНСГЛЮТАМІНАЗИ НА МОДЕЛЬНИХ ЗРАЗКАХ РЕСТРУКТУРОВАНИХ ШИНОК З ЯЛОВИЧИНИ

Науково-практичне рішення проблеми перетворення реструктурованої м’ясної системи до теплової обробки з отриманням структурних якостей цільном’язової тканини є актуальною задачею розвитку сучасної технології як науки про м'ясо. При вивченні даної проблеми найкращий результат був досягнутий при використанні ферментних препаратів, і в першу чергу ферменту трансглютамінази. Мікробіальна трансглютаміназа в кількості 0,075% забезпечує реструктурованим продуктам монолітність і покращує здатність їх до нарізання. Проведені раніше наукові дослідження підтвердили той факт, що трансглютаміназа також здатна підвищувати функціональність сироваткових білків у продуктах із подрібненого м’яса. Для досліджень були виготовлені дослідні зразки реструктурованих шинок з яловичини 1 сорту із заміною м’ясної сировини 3,0; 4,5; 6,0; 7,5% гідратованим білковим препаратом «Drip free cas». Раціональною кількістю, що сприяє покращенню структурно-механічних характеристик реструктурованих шинок, є внесення 0,075% трансглютамінази та 0,15% харчових фосфатів при заміні 6% м’ясної сировини сироватковим білковим препаратом «Drip free cas». Проведені дослідження підтвердили той факт, що розчини 0,065%, 0,075% та 0,085% трансглютамінази проявляють буферні властивості та стабілізують значення рН модельних м’ясних систем в процесі масажування, підвищують вологозв’язуючу здатність, а внесення трансглютамінази в кількості 0,075% сприяє збільшенню напруги різання дослідних зразків шинок на 7,7% у порівнянні із зразками, які містять 0,065% фермента.

영상 디코더의 제한된 버퍼를 고려한 전력 최소화 DVFS 방식

DVFS (Dynamic Voltage and Frequency Scaling) 에 기초한 저전력 기법은 배터리를 사용하는 모바일 장치에서 동작시간 향상을 위하여 매우 중요하다. 본 연구에서는 DVFS기법에 기반을 둔 영상디코더의 에너지 소비를 최소화핸 스케줄링 알고리즘을 제안 한다 특히, 기존연구에서 간과된 디코더와 디스플레이 사이에 위치한 버퍼의 크기 제약을 모델에 포함하여 버퍼 넘침을 방지 하도록하며, 이 모델에서 수학적으로 에너지를 최소화하는 알고리즘을 제안하고 증명하였다. 실제 영상을 통한 시뮬레이션 결과 버퍼의 크기가 10 프레임정도에서 이득이 포화상태가 되며, 제안된 알고리즘이 기존의 직관적인 알고리즘들에 비하여 평균 10% 정도의 전력소모 절약을 얻을 수 있음을 확인하였다. Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.

A No-Reference Quality Assessment System for Video Streaming over RTP

In the paper a no-reference system for quality assessment of video streaming over RTP is proposed for monitoring the quality of networked video. The proposed system is composed of four modules, where the quality assessment module utilizes information extracted from the bit-stream by the modules of RTP header analysis, frame header analysis and display buffer simulation. Taking MPEG-4 encoded video stream over RTP as an example, the process of video quality assessment using the proposed system is described in this paper. The proposed system is featured by its high efficiency without sorting to the original video or video decoding, and therefore well suited for real-time networked video applications.

Compression-Aware Energy Optimization for Video Decoding Systems With Passive Power

The objective of dynamic voltage scaling (DVS) is to adapt the frequency and voltage for configurable platforms to obtain energy savings. DVS is especially attractive for video decoding systems due to their time-varying and highly complex workload and because the utility of decoding a frame is solely depending on the frame being decoded before its display deadline. Several DVS algorithms have been proposed for multimedia applications. However, the prior work did not take into account the video compression algorithm specifics, such as considering the temporal dependencies among frames and the required display buffer. Moreover, the effect of the passive (leakage) power when performing DVS for multimedia systems was not explicitly considered. In this paper, we determine the optimal scheduling of the active and passive states to minimize the total energy for video decoding systems. We pose our problem as a buffer-constrained optimization problem with a novel, compression-aware definition of processing jobs. We propose low-complexity algorithms to solve the optimization problem and show through simulations that significant improvements can be achieved over state-of-the art DVS algorithms that aim to minimize only the active power.

Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player

We propose a low cost and stand-alone platform-based SoC for H.264/AVC decoder, whose target is practical mobile applications such as a handheld video player. Both low cost and stand-alone solutions are particularly emphasized. The SoC, consisting of RISC core and decoder core, has advantages in terms of flexibility, testability and various I/O interfaces. For decoder core design, the proposed H.264/AVC coprocessor in the SoC employs a new block pipelining scheme instead of a conventional macroblock or a hybrid one, which greatly contribute to reducing drastically the size of the core and its pipelining buffer. In addition, the decoder schedule is optimized to block level which is easy to be programmed. Actually, the core size is reduced to 138 KGate with 3.5 kbyte memory. In our practical development, a single external SDRAM is sufficient for both reference frame buffer and display buffer. Various peripheral interfaces such as a compact flash, a digital broadcast receiver and a LCD driver are also provided on a chip.

An XML-based approach to automated software testing

The advantages of automating the functional testing of application software are well-known, but the manner of automation can lead to difficulties in authenticating the test coverage. In this paper we consider the class of automated tests in which a driver tool simulates the input and responses of a human operator and sequentially checks the output generated by the application software. The driver tool commonly employs its own language to describe the tasks it can be required to perform, for example:• Issue a sequence of characters that simulate input from the keyboard.• Verify that a segment of the display buffer contains the expected bit pattern.Although these tasks are simply stated, the language to effect them in a test script can become complex and hard to maintain. Furthermore, reading the driver tool program is not an effective way to confirm that the test script performs its tasks to the test specification.XML (eXtensible Markup Language)[1)] scripts offer a rigorous intermediate description that can be readily translated into both the driver tool test script and a readable statement of the task the test performs. The advantages accruing from the use of XML are:• The XML scripts are easy to edit, simplifying basic script maintenance. New steps can be included for testing bug fixes.• Content review becomes much easier, as the relevant aspects of the script can be rendered in a readily readable form, such as HTML;• Global changes become feasible, as the structured nature of XML documents makes it possible to search for specific element content;• The structure of the XML document can itself be checked, for example using a validating editor such as Xeena [2)].In the next section we describe an example of automated testing using a driver tool, based on XML scripts. The application being tested is called Wired for Learning [3)] and provides the IT infrastructure for schools to:• Enhance communication between teachers, students and parents.• Enable teachers to plan and share ideas for lessons and activities, linking in with national standards.• Organize team projects involving teachers and students across classes and schools, with the option of inviting members of the community to provide additional information.• Provide an events calendar to keep everyone up to date with what is happening in the school.• Allow teachers easily to create their own home pages for information dissemination.

A single chip microcomputer for A/V monitor and TV receiver

A new application-specific microcomputer (MCU) designed to offer a user-friendly menu-driven on-screen display (OSD) in a multistandard A/V monitor and TV receiver is described. Built-in dedicated hardware is used to input the remote control signals. A single row display buffer requiring considerable CPU time is adopted for the on-screen display to conserve die size. A hardware multimaster inter-IC (IIC) bus interface is also available to facilitate computer alignment and troubleshooting during production or field service. The advanced features for next-generation TV MCU are also discussed. This MCU contains more than 120 K transistors and is fabricated in 1.5- mu m HCMOS technology with a die size of 45 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Stacked frame buffer algorithm for fast recovery of solid synthesis process

Fast recovery in solid modelling design is an important aid for users of CAD systems. A stacked frame buffer algorithm for solid modelling is proposed. This buffer is constructed as a multiframe array whose cells are maintained in an order according to priority of procedure linked to each pixel in terms of x and y elements on the image plane, so that the cells' contents may describe the visibility of current objects as well as the history of visible ones through the modelling process. The algorithm directly processes image data in the display buffer as it runs and recovers step-by-step. Using this method, problems of rapidly recovering from inadvertent operating errors and immediately modifying objects in the CAD process are solved.

New Products

The VAXstation 100 from Digital Equipment Corporation is the first in a family of high-performance video workstations intended for use with the company's VAX family of 32-bit computers. Featuring a 19-inch, high-resolution, monochrome, 60-Hz noninterlaced raster display and 103-key keyboard, a local display processor with display buffer, and a pointing device, the VAXstation 100 connects via fiber optics to any VAX computer system through a Unibus interface capable of supporting two workstations.

Microcomputer display timing: Problems and solutions

The 525-line composite video display standard is described and discussed from the viewpoint of its usefulness in psychology experiments. While a frame is displayed every 33.3 msec, it consists of two interlaced 262.5-line subframes displayed in 16.7 msec each. Thus, a display consisting of 16 or fewer video lines may be presented in 1 msec or less. The hardware of some microcomputers may be modified to make the video vertical synchronization timing signal available to latency timing software. This modification permits response signal and latency timing with 1-msec or better precision. A modification that permits display blanking under software control is also noted, and a detailed description of both modifications is given for the popular APPLE II microcomputer. Other problems discussed include moving display materials into display buffer areas in time for single-scan precision timing, software speed problems, and the tradeoffs between video and light-emitting diode displays.

A microprocessor display controller for combining refresh and storage tube graphics

This paper describes a stand alone graphics system utilizing a microprocessor based display controller with the capability of combining refresh with storage tube graphics. This combination is accomplished by utilizing the Write-Thru feature of a Tektronix 4014 display terminal. The display controller is a typical Z-80 microprocessor system interfaced to the 4014 by a standard Tektronix parallel interface. A portion of the Z-80 memory is used as the display buffer, allowing it to be divided into store and non-store (refreshed) segments. The microprocessor performs the conversion from the simple integer X, Y coordinates in the display buffer to actual Tektronix drawing commands. A second Z-80 microprocessor is used to perform graphical transformations and transfer the data from the PDP-11 host to the Z-80 display controller. The operations performed by the second microprocessor include translation, rotation and scaling. These operations are implemented by matrix multiplication of the user data by a user specified transformation matrix. The stand alone capabilities of the graphics system is made complete with interactive devices such as a tablet, analog dials, and function switches interfaced directly to the host computer.

Computer-assisted measurement system for x-ray films of the vocal tract.

Measurements on sagittal X rays of the vocal tract may be made directly in terms of the variables of an articulatory model by superimposing a computer-generated vocal-tract outline onto the x-ray image. Previous methods require an operator to trace a pen or pointer coupled to a recording device along the outlines or the projected image. The new system uses two video signals, one derived from a television camera scanning the projected x-ray image, the second from data in a computer display buffer. The computer display is modified through adjustment of control potentiometers assigned to the model variables. Convergence to a match between the two images is found to be a substantially quicker and easier task than manually tracing the image outline.

Computer-Assisted Measurement System for X-ray Films of the Vocal Tract

Measurements on sagittal x rays of the vocal tract may be made directly in terms of the variables of an articulatory model by superimposing a computer-generated vocal-tract outline onto the x-ray image. Previous methods require an operator to trace a pen or pointer coupled to a recording device along the outlines of the projected image. The new system uses two video signals, one derived from a television camera scanning the projected x-ray image, the second from data in a computer display buffer. The computer display is modified through adjustment of control potentiometers assigned to the model variables. Convergence to a match between the two images is found to be substantially quicker and easier task than manually tracing the image outline.