Direct Memory Access Transfer Research Articles

Optimizing Inter-Core Communications Under the LET Paradigm using DMA Engines

Modern automotive applications are increasingly characterized by the need to transfer massive amounts of data in a predictable and deterministic way, possibly leveraging the Logical Execution Time (LET) paradigm. However, current proposals for LET communications are limited to core-commanded data transfers, which may result in large delays for data-intensive systems. To address this issue, we explore the use of Direct Memory Access (DMA) to handle LET communication with improved parallelism. Each DMA transfer operates on a contiguous memory area, thus calling for an optimized memory mapping to maximize performance. Modern DMA engines offer also advanced configurations, such as linked-lists of data transfers, which may provide more flexibility at the expenses of an increased (initial) programming overhead. Leveraging all such features of DMA engines, we propose a set of designs and protocols for LET communications with trade-offs between latency and space requirements. For each option we present the formulation to compute the optimal scheduling and memory allocation solution as a mixed-integer linear programming problem. Experimental results show the feasibility of the approach and a comparison of the solutions obtained using the proposed methods, showing a considerable improvement in terms of data acquisition latency when compared to LET communication without DMA.

Research and Application of High-Speed and Adjustable Synchronous Data Transfer System Based on USB 3.0 Peripheral Controller

Since bulk transfer bandwidth of the host is unstable, the universal serial bus (USB) 3.0 hyperspectral data transfer system can only achieve a data transfer rate of about 30 MBps which is less than one-fifteenth of USB 3.0 theoretical transfer rate of 5 Gbps. For aerial hyperspectral imager, data transfer system is required to meet different frame rates of detector for different speed-to-height ratios. In this paper, we propose a high-speed and adjustable synchronous transfer system. The USB 3.0 peripheral controller uses synchronous first in first out (FIFO) and automatic direct memory access (DMA) to achieve the highest data transfer bandwidth. The USB acquisition software collects a data block in every fixed time interval. The size in bytes of every data block must be an integer multiple of the maximum data packet payload size, which is a necessary condition for using automatic DMA and bulk transfers. The data transfer rate of the system could be adjusted by directly changing the data block size and acquisition time interval. The experimental results show that the synchronous transfer mechanism could facilitate the 100-MBps error-free and high data transfer bandwidth application on a hyperspectral data processing system.

Focus on analytical equipment, sensors, and instrumentation

Focus on analytical equipment, sensors, and instrumentation

CubeDMA – Optimizing three-dimensional DMA transfers for hyperspectral imaging applications

Onboard computing is one of the principal needs in space-related technology in the recent years. In particular, onboard hyperspectral imaging (HSI) processing has advanced significantly. Due to advances in sensor technology, onboard HSI processing continuously meets new challenges related to increasing dataset size, limited processing time and limited communication links. High throughput and data reduction are crucial for satisfying real-time constraint and for preserving transmission bandwidth. For systems capable of accommodating a wide range of processing algorithms, there is a need for a flexible communication infrastructure that can provide fast access to/from memory in different access patterns. In this paper, existing FPGA-related Direct Memory Access (DMA) solutions have been evaluated, and a new DMA solution tailored for hyperspectral images has been proposed. Results show that the proposed DMA core, CubeDMA, handles targeted memory access patterns in more efficient manner than existing solutions while being resource efficient.

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

With a growing number of cores integrated in a single chip, the efficiency of inter-core direct memory access (DMA) transfers has an increasingly significant impact on the overall performance of parallel applications running on network-on-chip (NoC) processors. In this paper we propose HyDMA, a low-latency inter-core DMA approach based on a hybrid packet-circuit switching NoC. With dynamic setup and lengthening of circuit channels composing of bidirectional links, HyDMA can achieve both high flexibility of packet switching and low communication latency of circuit switching for concurrent DMA transfers. Experimental results prove HyDMA exhibits high efficiency with marginal hardware overhead.

Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors

In this article, we propose a heuristic algorithm for scheduling synchronous data flow (SDF) models on scratch pad memory (SPM) enhanced processors with the objective of minimizing its steady-state execution time. The task involves partitioning the limited on-chip SPM for actor code and data buffer, and executing actors in such a manner that the physical SPM is time shared with different actors and buffers (formally defined as code overlay and data overlay, respectively). In our setup, a traditional minimum buffer schedule could result in very high code overlay overhead and therefore may not be optimal. To reduce the number of direct memory access (DMA) transfers, actors need to be grouped into segments. Prefetching of code and data overlay that overlaps DMA transfers with actor executions also need to be exploited. The efficiency of the our heuristic was evaluated by compiling ten stream applications onto one synergistic processing engine (SPE) of an IBM Cell Broadband Engine. We compare the performance results of our heuristic approach with a minimum buffer scheduling approach and a 3-stage ILP approach, and show that our heuristic is able to generate high quality solutions with fast algorithm run time.

Optimizing two-dimensional DMA transfers for scratchpad Based MPSoCs platforms

Reducing the effects of off-chip memory access latency is a key factor in exploiting efficiently embedded multi-core platforms. We consider architectures that admit a multi-core computation fabric, having its own fast and small memory to which the data blocks to be processed are fetched from external memory using a DMA (direct memory access) engine, employing a double- or multiple-buffering scheme to avoid processor idling. In this paper we focus on application programs that process two-dimensional data arrays and we determine automatically the size and shape of the portions of the data array which are subject to a single DMA call, based on hardware and applications parameters. When the computation on different array elements are completely independent, the asymmetry of memory structure leads always to prefer one-dimensional horizontal pieces of memory, while when the computation of a data element shares some data with its neighbors, there is a pressure for more “square” shapes to reduce the amount of redundant data transfers. We provide an analytic model for this optimization problem and validate our results by running a mean filter application on the Cell simulator.

DMA transfer method for wide-range speed and frequency measurement

A frequency measurement method based on both pulse counting and time measurement during a constant sampling time is presented. The content of a free-running timer is transferred by a direct memory access (DMA) to a memory location after each rising edge of an input pulse, so the DMA transfer counter serves as a pulse counter. Several sources of measurement errors are discussed in detail. The DMA method is suitable for real-time speed control system with an integrated DMA controller. >

Speed measurement using the improved DMA transfer method

A wide-range speed measurement method using the direct memory access (DMA) transfer of a content of the timer to the memory is presented. The DMA method is based on both pulse counting and time measurement during the constant sampling time. The hardware configuration and algorithms for a microcontroller implementation are also presented. The proposed method is suitable in systems using microcontrollers with integrated DMA controller and timers. Limitations and sources of errors are discussed in detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Specialized module for full frame radiological image compression

The full-frame image compression technique was developed at the University of California, Los Angeles, specifically for radiological applications. Because this method is very innovative and unique, no commercially available hardware is able to process the algorithm with any efficiency. We have developed a dedicated hardware module for this purpose based on the latest technology. Specifications were determined from clinical requirements. Various important technical challenges were overcome by customized system designs, including a key concept of using dual-bus architecture for direct memory access transfer. We report on the status of a functional prototype and some image quality evaluations.

A pulse generating and data recording system based on the microcomputer PDP 11/23

A widely applicable measuring system, especially suited for all types of ‘voltage-clamp’ (including ‘patch-clamp’) experiments, is presented. It is mainly based on commercially available hardware and software components. All interfacing with the analog world takes place on the front panel of the microcomputer box. Synchronization of pulse generation with data acquisition and other control actions take advantage of the four upper bits not used by the digital-to-analog converter during direct memory access transfer.

Positron Camera-Computer System for Various Section Images

A multicrystal positron camera (MGH type) has been constructed for diagnostic investigation with shortlived positron emitters produced by the NIRS cyclotron. In order to use this camera clinically and experimentally a computer system has been constructed for data collection, reconstruction, image processing, display and driving optional terminals. Since the speed of data collection must be as fast as possible for the dynamic image collection, direct memory access transfer mode are selected for data Timing signals and physiological data are multiplexed with detected event data. For the clinically suitable image display a display terminal with a fine pixel size has been constructed which can be also available to display a fine image such as x-ray CT images. A rotating disc chair has been constructed for transverse section image construction with the positron camera. The chair is automatically controlled by a host minicomputer.