Direct Down-conversion Mixer Research Articles

A 60 GHz Current-Reuse LO-Boosting Mixer in 90 nm CMOS

This letter presents a 60 GHz direct down-conversion mixer in a 90 nm CMOS. The mixer consists of an RF transconductance stage, a switching stage, an LO amplification stage, a balun and a buffer amplifier, and employs a current-reuse LO-boosting technique for low power consumption with small LO input power. The measured conversion gain of the differential IF output is 12 dB at an input LO power of -13 dBm. The mixer consumes 8.8 mW and the measured 3 dB IF bandwidth is greater than 1.2 GHz. To the best of our knowledge, this mixer achieves the highest conversion gain with the lowest LO input power of all published 60 GHz band CMOS mixers.

Mismatch reduction technique for transistors with minimum channel length

An analog calibration technique is presented to improve the parameter matching between transistors in the differential high-frequency signal path of analog CMOS circuits. It can be applied for mismatch reduction in differential broadband amplifiers and direct down-conversion mixers in which short-channel devices are utilized to minimize bandwidth reduction from parasitic capacitances. In general, the proposed methodology is suitable for radio frequency (RF) applications in which direct matching of the transistors is undesired because sophisticated layout practices would increase the coupling between the high-frequency paths. The approach involves auxiliary devices which sense the existing mismatch as part of a feedback loop for error minimization. This technique is demonstrated with a differential amplifier that has a loaded gain and ?3 dB frequency of 12.9 dB and 2.14 GHz, respectively. It was designed in 90 nm CMOS technology with a 1.2 V supply. Monte Carlo simulations indicate that the 4.06 mV standard deviation of the amplifier's anticipated input-referred offset voltage improves to 0.76---1.28 mV with the mismatch reduction loop, which is contingent on the layout configuration of the calibration circuitry. The associated drain current mismatch reduction for the transistor pair under calibration in the amplifier core is from 3.1% to 0.6---1.0%.

Wideband direct downconversion Gilbert mixer for 60 GHz applications

The design and the measurement results of a direct downconversion mixer for the 60 GHz ISM band are presented. Based on a Gilbert structure, the mixer is optimised for high bandwidth and designed in a 180 GHz SiGe technology. Without any buffer stages, the measured conversion gain is Gconv=−7 dB. The remarkably high IF bandwidth allows downconverting a continuous band of 15 GHz with flatness of ±1.4 dB and enables the design of ultra-high data rate transceivers.

A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS

The design of RF integrated circuits, at the low voltage allowed by sub-scaled technologies, is particularly challenging in cellular phone applications where the received signal is surrounded by huge interferers, determining an extremely high dynamic range requirement. In-depth investigations of 1/f noise sources and second-order intermodulation distortion mechanisms in direct downconversion mixers have been carried out in the recent past. This paper proposes a fully integrated receiver front-end, including LNA and quadrature mixer, supplied at 750 mV, able to meet GSM specifications. In particular, the direct downconverter employs a feedback loop to minimize second-order common mode intermodulation distortion, generated by a pseudo-differential transconductor, adopted for minimum voltage drop. For maximum dynamic range, the commutating pair is set with an LC filter. Prototypes, realized in a 90-nm RF CMOS process, show the following performances: 51 dBm IIP2, minimum over 25 samples, 1 dB desensitization point due to 3-MHz blocker at -18 dBm, 3.5 dB noise figure (NF), integrated between 1 kHz-100 kHz, 15 kHz 1/f noise corner. The front-end IIP2 has also been characterized with the mixer feedback loop switched off, resulting in an average reduction of 18 dB.

A High Performance CMOS Direct Down Conversion Mixer for UWB System

This paper presents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18μm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528 MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.

Resolving fundamental issues of slowness in envelope simulation methods

Fourier-envelope algorithms are an important component of the mixed-signal/RF verification toolbox. In this article the unpredictability and lack of robustness that has been reported for these algorithms is addressed. It is shown that the problem stems from “slow” envelopes that fundamentally feature fast oscillations. We demonstrate that this is related to the fact that the envelope equations are always stiff, whether or not the underlying system is. We show that careful choice of the envelope initial conditions is necessary to obtain useful solutions, and propose two techniques for finding good initial conditions. By applying these techniques and solving the envelope equations with stiffly-stable numerical methods, we obtain a robust and reliable Fourier-envelope method. The new methods are illustrated by a direct-downconversion mixer circuit. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2005.

An UTRA/FDD Direct-Downconversion Mixer in 0.25 μm CMOS

In this paper the design of a 2 GHz direct-downconversion mixer for a UTRA/FDD receiver is presented. The mixer is implemented using a standard low-cost 0.25 μm, single-poly, six-metal CMOS process. An on-chip passive balun is used to generate a balanced RF input signal. In-house optimized device models are used for both active and passive components to achieve a voltage conversion gain of 12.8 dB, an iIP2 of 25 dBm, an iIP3 of −3.1 dBm, and a noise figure of 8 dB. The circuit provides I and Q signal path outputs while drawing 6 mA from a 2.5 V supply.