Direct Down-conversion Receivers Research Articles

Spectrum Sensing in SIMO Cognitive Radios Under Primary User Transmitter IQ Imbalance

In this paper, we model the received signal of a single-input-multiple-output (SIMO) cognitive radio with in-phase and quadrature imbalance (IQI) in the transmitter. Then, the spectrum sensing problem is formulated as a composite hypothesis testing problem. We propose two new eigenvalue-based detectors based on the likelihood ratio test (LRT), Rao and Wald frameworks, i.e., the resultant LRT leads us to the Wald test. For the proposed Rao test, we find closed-form expressions for false alarm and detection probabilities under noise variance uncertainty in order to get the level of desired false alarm probability $p_{\text{fa}}$ , i.e., it is called a level $p_{\text{fa}}$ test. This is required for nonconstant false alarm rate (non-CFAR) such as the Rao test to guarantee that the obtained false alarm rate is always below a required level $p_{\text{fa}}$ . Additionally, an analytical formula for the probability of false alarm of Wald test is presented to confirm our simulation results. In this case, the proposed Wald detector is a size $p_{\text{fa}}$ test, called a CFAR detector. Detection performances of the proposed detectors are compared in different scenarios by extensive Monte Carlo simulations. It is shown that the Wald detector outperforms the proposed Rao one. Also, we show that the effects of transmitting IQI can be considered as a signal-to-noise ratio factor, just affecting the detection performance. Also, our performance results show that the proposed Wald detector is fairly robust to the receiver IQI when direct down-conversion receivers are exploited.

Clock Jitter Compensation in High-Rate ADC Circuits

Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acquired samples in the midst of random noise. We propose low-complexity digital signal processing methods for estimating the jitter in real-time for direct downconversion receivers at high sampling rates. We also propose adaptive compensation methods for the jitter and analyze the performance of the proposed techniques in some detail as well as through simulations.

Architectural solution for second-order intermodulation intercept point improvement in direct down-conversion receivers

Second-order intermodulation is a great drawback in zero-intermediate frequency (IF) receivers. Many complex techniques for distortion cancelling have been proposed in the literature. In this study, the authors propose a simple architectural solution for second-order intermodulation intercept point (IIP2) improvement and also theoretically and experimentally demonstrate the high rejection level abilities. To determine its performance, a classical in-phase and quadrature (IQ) demodulator was also designed and used as a reference. In order to compare their non-linear behaviour in the presence of interfering signals, two types of zero-IF demodulators were tested in this work in terms of error vector magnitude and bit error rate. This study shows that by using the three-phase architecture it is possible to gain 20 dB in blocking effect rejection in comparison to the classical IQ architecture.

DE-INTERLEAVED SUBSAMPLING ARCHITECTURE FOR HOMODYNE RECEIVERS

This paper presents a de-interleaved subsampling receiver architecture suitable for homodyne receivers. The proposed topology requires only a single branch to down-convert and extract the in- phase (I) and quadrature (Q) baseband signals. Using a single- branch receiver eliminates the I=Q mismatch issue of traditional direct down-conversion receivers. The simplicity of the proposed receiver architecture makes it an alternative solution for multi-band and multi- standard applications.

Improved four-channel direct-conversion SiGe receiver IC for UMTS base stations

This work presents the design and measurement results of an improved four-channel, direct down conversion receiver (DCR) for the application in universal mobile telecommunications system base stations. The whole analog receiver functionality including low noise amplifier, variable gain amplifier, local oscillator frequency divider, in-phase and quadrature DCR mixers and seventh-order active lowpass filter is integrated using Atmel's 50-GHz f/sub t/, 50-GHz f/sub max/ SiGe foundry technology (Atmel, 1998). Important cascaded design parameters of the fully ESD-protected device are a noise figure 1.5 to 2 dB; IIP3 (third-order intercept point) -20.3 to -15.8 dBm and a voltage gain of 51 to 57 dB into a 1000-/spl Omega/ /spl par/ 2.5-pF differential load [analog to digital converter].