Direct Digital RF Modulator Research Articles

A Wideband Linear <inline-formula> <tex-math notation="LaTeX">$I/Q$ </tex-math> </inline-formula>-Interleaving DDRM

This paper presents a wideband linear direct-digital RF modulator (DDRM) in 40-nm CMOS technology. An innovative $I/Q$ -interleaving RF digital-to-analog converter (DAC) is proposed to enable the combination of in-phase ( $I$ ) and quadrature ( $Q$ ) signals in a more digital fashion, thereby improving the linearity performance at large bandwidths. The DDRM also features an advanced second-order hold digital interpolation filter to suppress the sampling spectral replicas in the presence of large bandwidth signals. Moreover, the harmonic rejection technique in the context of RF DAC operation is adopted and implemented. The $2 \times 9$ -bit DDRM core occupies 0.21 mm2 and consumes 110 and 146 mW at 1 and 3 GHz, respectively, with the peak power of +9.2 dBm. The error vector magnitude (EVM) and adjacent channel power ratio (ACPR) at 3 GHz for a 57-MHz 64-QAM signal are better than −30 and −45 dB, respectively, and ACPR remains as low as −44 dBc up to a wide bandwidth of 113 MHz.

Direct-digital RF-modulator: a multi-function architecture for a system-independent radio transmitter

The number of different radio systems is currently increasing in portable devices like mobile phones due to the wider range of applications that require an optimized wireless communications channel to different services or other devices. To make this cost and power efficient, the transmitter must be adaptable to several different radio systems while keeping the complexity and cost reasonable. This article presents fundamental circuit techniques to enable low cost, low power, and low complexity transmitter architecture by combining digital-to-analog conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image rejection filtering into a single mixed-signal circuit block. The direct-digital RF-modulator architecture is the basis for a software-defined radio transmitter. It was demonstrated against WCDMA system requirements, but the versatility and the performance of this architecture enables support for other radio systems, such as GPRS and WLAN.

A Multimode Transmitter in 0.13 $\mu\hbox{m}$ CMOS Using Direct-Digital RF Modulator

This paper presents a system-independent transmitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block. The multimode capability of the architecture is demonstrated with WCDMA, EDGE, and WLAN system requirements. The modulator achieves 90 dB of power control range and with an external power amplifier module, WCDMA EVM of less than 2% from signal powers of -20 dBm to +25 dBm. The noise floor level defined by the quantization noise at 190 MHz offset from the carrier is -150 dBc/Hz measured at the output of the PA with +25 dBm signal power. The analog power consumption with the maximum signal power level is 92 mW and scales down to 46 mW when reducing the signal level to -43 dBFS. The digital power consumption is 65 mW. The chip is implemented with a standard 0.13 mum 1.2 V digital CMOS with total silicon area of 4 mm2.