Direct Digital Frequency Synthesizer Design Research Articles

An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

Direct Digital Frequency Synthesizer Design and Implementation on FPGA

Direct Digital Frequency Synthesizer Design and Implementation on FPGA

High-performance DDFS design using the equi-section division method

In this paper, an equi-section division method utilizing the symmetry property and amplitude approximation of a sinusoidal waveform to design a direct digital frequency synthesizer (DDFS) is proposed. The sinusoidal phase of a one-quarter period is divided into equi-sections. The error value between each line segment value and the sinusoidal amplitude value is stored in a read-only memory (ROM) to reconstruct the real sinusoidal waveform. The upper/lower bound of the maximum error value stored in error-compensation ROM will be derived to determine the minimum required memory wordlength relative to the bit number of the equi-sections. In addition, the minimum size of the total ROMs can be computed according to the bit number of the equi-sections. Thus, the equi-section division method is implemented on a field programmable gate array (FPGA) development board. As a result, the total compression ratio of the DDFS using the equisection division method is superior to that of the DDFS using the traditional compression methods. The simulation and experimental results show that the proposed ROM compression method can effectively achieve a better compression ratio and lower complexity, compared with the DDFS using the traditional compression methods, without affecting the spectrum performance.

A direct digital frequency synthesizer with high-speed current-steering DAC

A high-speed SiGe BiCMOS direct digital frequency synthesizer (DDS) is presented. The design integrates a high-speed digital DDS core, a high-speed differential current-steering mode 10-bit D/A converter, a serial/parallel interface, and clock control logic. The DDS design is processed in 0.35 μm SiGe BiCMOS standard process technology and worked at 1 GHz system frequency. The measured results show that the DDS is capable of generating a frequency-agile analog output sine wave up to 400+ MHz.

A high‐SFDR direct digital frequency synthesizer with embedded error‐compensation CMOS OTP ROM for wireless receivers

AbstractA direct digital frequency synthesizer (DDFS) using on‐chip CMOS one‐time programmable read‐only memory (OTP ROM) is presented. A straight‐line approximation algorithm for sinusoid with compensation is adopted such that the accuracy could be maintained and the cost is reduced. Most important of all, a CMOS OTP ROM is used as a look‐up ROM table, which is implemented by a typical logic CMOS process. Therefore, the proposed DDFS can be integrated in any CMOS‐based front‐end circuit for wireless communication systems. The proposed DDFS design is fully implemented using a typical 1P6M 0.18 μm CMOS process. It has a 12‐bit amplitude resolution with 86.89 dB spurious free dynamic range using a small ROM size of 256 bits. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1695–1699, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24422