Direct Digital Frequency Synthesizer Architecture Research Articles

Comparison between Trigonometric, and traditional DDS, in 90 nm technology

The Direct Digital frequency Synthesizer (DDS) is an architecture largely used for the generation of numeric sine and/or cosine waveforms in different applications. In this work, authors compare two different DDS architectures: the traditional architecture, based on the exploitation of quarter wave symmetry, and the Symon’s DDS (trigonometric DDS) presented in 2002. The two layout configurations have been implemented in 90 nm technology and compared in terms of area, speed and power consumption. Comparisons have been performed in terms of circuital complexity on architectures having the same Spurious Free Dynamic Range (SFDR) and phase resolution. Experiments show that the trigonometric architecture is very efficient in terms of area.

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems.The recent literature proposes various DDFS implementation techniques that, implemented by using state of the art Application Specific Integrated Circuits (ASIC) technologies, provide ever improving performances in terms of speed, power dissipation and silicon area occupation.The performance trend provided by the advanced designs that target ASIC technologies is not guaranteed to remain the same when the target technology is a commercially available Field Programmable Gate Array (FPGA) device.This paper presents the FPGA implementation of the best performing DDFS architectures proposed to date. DDFS performance trends are compared with the ASIC implementations. Further, the state of the art DDFS circuits are modified in order to better suit the FPGA technology and compared against the DDFS implementations obtained using Intellectual Properties (IPs) included in the design suites of the FPGA manufacturers. The comparison is conducted considering as implementation target various (both low end, middle range, and high end) FPGA devices produced by different vendors. Considered performance parameters are the maximum working frequency, the dynamic power dissipation, the logic resource occupation, and the precision of the DDFS measured in terms of Spurious Free Dynamic Range (SFDR).The analysis shows that when dealing with FPGA implementations, it is important that the implemented architectures adapt to the internal logic resources of the FPGA. For low SFDR values the best performing architectures are the straightforward ROM based ones that optimally fit in the very fast Block RAM of the FPGA. When the required SFDR increases more advanced architectures are required. The optimal architectures also depend on the design choice of privileging high working frequency or reduced power dissipation.

A novel ROM compression architecture for DDFS utilizing the parabolic approximation of equi-section division

In this paper, we propose the parabolic approximation of equi-section division (PAESD) utilizing the symmetry property and amplitude approximation of a sinusoidal waveform to design a direct digital frequency synthesizer (DDFS). The sinusoidal phase of a one-quarter period is divided into equi-sections. The proposed method utilizes the curvature equivalence to derive each parabolic curve function, and then the value of the error function between each parabolic curve function and the sinusoidal function is stored in an error-compensation ROM to reconstruct the real sinusoidal waveform. The upper/lower bound of the maximum error value stored in the error-compensation ROM is derived to determine the minimum required memory word length relative to the number of bits of the equi-sections. Thus, the minimum size of the total ROMs of the DDFS using the PAESD without error-compensation ROM is compressed to 544 bits; the total compression ratio, compared with the minimum size of the total ROMs of the DDFS using the basic look-up table (LUT), is approximately 843:1, achieved by consuming additional circuits [71 adaptive look-up tables (ALUTs), 3 digital signal processor (DSP) block 9-bit elements]. Consequently, the results show that the proposed ROM compression method can effectively achieve a better compression ratio than the state-of-the-art solutions without affecting the spectrum performance of an average spurious-free dynamic range (SFDR) of -85 dBc.

Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation

This paper investigates a novel direct digital frequency synthesizer architecture, based on piecewise linear approximation with segments of nonuniform length. The new approach allows reducing the total number of segments with respect to the well-known uniform segmentation. In this way the size of the coefficient ROM is also reduced with beneficial effects in terms of speed and power. We show that the optimal nonuniform segmentation (that maximizes the spurious-free dynamic range for a given number of nonuniform segments) can be obtained as the solution of a mixed-integer linear programming problem. Three simple, suboptimal, nonuniform segmentation schemes (which lend themselves to efficient hardware implementation) are proposed in this paper. We present also several design examples and VLSI implementation results, which demonstrate the effectiveness of the developed technique.

A direct digital frequency synthesizer based on two segment fourth-order parabolic approximation

A novel design is presented about ROM-less direct digital frequency synthesizer (DDFS) using phase to sinusoid amplitude conversion blocks based on the two segment fourth-order parabolic approximation. The mathematical maximum error analysis shows that the resolution is up to 14 bits. In order to reduce the hardware complexity without sacrificing speed, the squarer and constant multipliers have been decomposed and optimized. The whole architecture has been split into twenty pipelining stages with a 200 MHz clock rate and a single phase output up to 50 MHz. Meanwhile, because the sine and cosine phase to amplitude modules share the same hardware, reduction of hardware complexity and power consumption can be achieved. Spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is about -90 dBc. The implementation demonstrates that the proposed DDFS architecture can be realized with a smaller hardware scale and lower power consumption than many other existing approaches.