Direct-coupled FET Logic Inverter Research Articles

Temperature-Dependent Study of AlGaAs/InGaAs Integrated Depletion/Enhancement-Mode High Electron Mobility Transistors with Virtual Channel Layers

Recently, we have implemented the direct-coupled FET logic inverters by the AlGaAs/InGaAs co-integrated depletion-mode (D-mode) and enhancement-mode (E-mode) pseudomorphic high electron mobility transistors (PHEMTs) with virtual channel layers in this journal. In this article, the temperature-dependent characteristics of the above integrated PHEMTs will be demonstrated. Due to the two-dimensional electron gas (2DEG) located in the undoped In0.22Ga0.78As layer between two large energy-gap Al0.24Ga0.76As barrier layers, the integrated devices exhibit excellent thermal stability for the good confinement effect in the 2DEG channel. Experimental results exhibit that the maximum transconductance decreases from 162.2 (174.4) to 125.0 (105.8) mS mm−1 for the studied D-mode (E-mode) device as the temperature increases from 300 to 450 K. In addition, the maximum drain current reduces from 366.4 (379.6) at 300 K to 286.4 (254.6) mA mm−1 at 450 K. Significantly, a considerably low temperature coefficient on threshold voltage (∂Vth/∂T) of −0.266 (−0.866) mV K−1 for the D-mode (E-mode) PHEMT is measured, which is superior to the previous reports of the related GaAs-substrate transistors.

Monolithic integration design of GaN-based power chip including gate driver for high-temperature DC–DC converters

Power integration is essential for the fully utilization of advanced GaN devices in power conversion applications due to the reduced parasitic inductance, low on-state resistance, and high-temperature operation. This paper presents a GaN-based monolithic integration design with optimized gate drivers for high-temperature DC–DC converters. Four different gate drivers are experimentally evaluated for integration with boost converters based on enhancement (E)-mode AlGaN/GaN metal–insulator–semiconductor heterojunction-field-effect-transistors (MIS-HFETs). The optimized gate driver, consisting of DCFL (Direct-Coupled FET Logic) inverters and a buffer amplifier, can operate over a wide temperature range (from 25 °C to 250 °C). Furthermore, a 100 kHz, 5 V/11 V (VIN/VOUT) boost converter prototype with the proposed monolithic integration design was built and found to operate successfully under high temperatures (HTs) up to 250 °C. These results validate the advantages of GaN-based monolithic integration techniques in achieving HT, high power density, and high efficiency power converters.

Monolithic integration of enhancement/depletion-mode high electron mobility transistors using hydrogen plasma treatment

We demonstrate a planar technique of hydrogen plasma treatment for monolithic integration of enhancement/depletion (E/D)-mode GaN high electron mobility transistors (HEMTs). By hole compensation mechanism, E-mode and D-mode HEMTs based on p-GaN/AlGaN/GaN heterojunctions are simultaneously realized on the same wafer. The fabricated direct-coupled FET logic inverter with a driver/load ratio of 10 exhibits a large output logic swing of 4.78 V, wide noise margins, an ultralow threshold hysteresis of 13 mV, and good temperature stability up to 300 °C, while the fabricated 11-stage ring oscillator shows a propagation delay of 0.8 ns/stage at VDD = 5 V.

Inverter Logic of AlGaAs/InGaAs Enhancement/Depletion-Mode Pseudomorphic High Electron Mobility Transistors with Virtual Channel Layers

In this article, the direct-coupled FET logic (DCFL) inverters are implemented by co-integrated AlGaAs/InGaAs depletion-mode and enhancement-mode pseudomorphic high electron mobility transistors with virtual channel layers, and the inverters with varying gate width of the depletion-mode transistors are demonstrated. The experimental results show that the drain current IDS (mA/mm) and gm (mS/mm) per unit gate width increases as the gate widths of the depletion-mode devices decrease. This is attributed to the fact that the drain current and transconductance values are related to the channel-to-source resistance and the source contact resistance. When the gate width is reduced, the source pad contact area is only slightly changed and the IDS (mA/mm) as well as the transconductance gm (mS/mm) will increase. In addition, it is also observed that for the reduce of the gate width of the depletion-mode devices, the transfer characteristics of the DCFL inverters are steep and shift to the left due to the smaller drain saturation current of the load transistor.

Digital Integrated Circuits on an E-Mode GaN Power HEMT Platform

GaN-based digital integrated circuits (ICs) are realized on a 6-inch GaN-on-Si power high-electron-mobility transistor (HEMT) platform by monolithic integration of enhancement/depletion-mode HEMTs using a 0.5- $\mu \text{m}$ gate technology. A direct-coupled FET logic inverter and a 101-stage ring oscillator are fabricated and characterized. The inverter exhibits a large input voltage swing, wide noise margin, and high temperature stability, while the ring oscillator features a small propagation delay of 0.1 ns/stage under a supply voltage of 4 V. These digital ICs can operate properly up to at least 200 °C and show great potential for GaN smart power IC applications.

Temperature dependence and thermal stability of planar-integrated enhancement/depletion-mode AlGan/GaN HEMTs and digital circuits

We report detailed results on the temperature dependence and thermal stability of the planar-integrated enhancement/depletion-mode (E/D-mode) AlGaN/GaN high-electron mobility transistors (HEMTs). Compared to the standard mesa etching technique, the plasma treatment can achieve the same device isolation results. The E/D-mode HEMTs and the corresponding digital integrated circuits fabricated by the planar process exhibit stable operation from room temperature up to 350 °C. No degradation in device performance was observed after a 140-h thermal stress at 350 °C, implying excellent thermal stability of the planar process. The direct-coupled FET logic inverter, realized by planar-integration of E/D-mode HEMTs, presents larger noise margins (NM S) at high temperatures than the previously reported work, demonstrating promising potential for GaN-based high-temperature digital ICs. The NM improvement can be attributed to the higher threshold voltage and the improved gate turn-on voltage of the E-mode HEMTs that is achieved with larger plasma treatment dose.

Device Isolation by Plasma Treatment for Planar Integration of Enhancement/Depletion-Mode AlGaN/GaN High Electron Mobility Transistors

We demonstrate a new planar fabrication technology for integrating enhancement/depletion (E/D) mode AlGaN/GaN high electron mobility transistors (HEMTs) using fluoride plasma treatment techniques. The CF4 plasma treatment is used in two separate steps to achieve two objectives: 1) active device isolation; and 2) threshold voltage control for the E-mode HEMT formation. Compared with the devices formed by standard mesa etching, the HEMTs by planar process have comparable DC characteristics, with no obvious difference in device isolation. By using the planar process, the E/D-mode HEMTs are integrated on the same chip, and a direct-coupled FET logic inverter and a 17-stage ring oscillator are fabricated. When the supply voltage is 4.5 V, the ring oscillator yields a frequency of 146 MHz, corresponding to a propagation delay of 201 ps/stage.

Planar integration of E/D-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment

A planar-fabrication technology for integrating enhancement/depletion (E/D)-mode AlGaN/GaN high-electron mobility transistors (HEMTs) has been developed. The technology relies heavily on CF/sub 4/ plasma treatment, which is used in two separate steps to achieve two objectives: 1) active device isolation and 2) threshold-voltage control for the enhancement-mode HEMT formation. Using the planar process, depletion- and enhancement-mode AlGaN/GaN HEMTs are integrated on the same chip, and a direct-coupled FET logic inverter is demonstrated. Compared with the devices fabricated by a standard mesa-etching technique, the HEMTs by a planar process have comparable dc and RF characteristics with no obvious difference in the device isolation. The device isolation by a plasma treatment remains the same after 400 /spl deg/C annealing, indicating a good thermal stability. At a supply voltage (V/sub DD/) of 3.3 V, the E/D-mode inverters show an output swing of 2.85 V, with the logic-low and logic-high noise margins at 0.34 and 1.47 V, respectively.

Analytical modeling of a DCFL inverter using normally-off GaAs MESFET’s under dark and illuminated conditions

An analytical model has been presented to study the characteristics of a DCFL (Direct Coupled FET Logic) inverter using normally-off GaAs MESFET’s (E-MESFET’s) under dark and illuminated conditions. Optical illumination is provided at the gate area of the MESFET with a transparent/semi-transparent metal at the Schottky junction of the device. The photovoltage developed across the Schottky junction due to the illumination may be used to control the characteristics of the inverter circuit. The transfer characteristics of the inverter with fanout = 0 and 1 have been presented under both the dark and illuminated conditions. It has been observed that the circuit may change its state from high to low logic level by simply changing the illumination level provided on the gate-area of the switching E-MESFET.

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFL circuit

High-speed 8:1 multiplexer and 1:8 demultiplexer ICs composed of GaAs direct-coupled FET logic (DCFL) have been designed and fabricated. The ICs were designed with a tree-type architecture and using memory-cell-type flip-flops (MCFFs). Self-aligned GaAs MESFETs with a gate length of 0.5 mu m were used in these ICs. The propagation delay time of the DCFL inverter was 19.0 ps/gate. Both ICs operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V. These ICs are applicable for multigigabit lightwave communication systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A GaAs Floated Electron Channel Field Effect Transistor (FECFET) Fabricated by Selective Metal Organic Chemical Vapor Deposition

We have proposed and fabricated a new GaAs FET with very short channel, which we call Floated Electron Channel Field Effect Transistor (FECFET), using the Selective Metal Organic Chemical Vapor Deposition (SMOCVD) technique. The channel length of the proposed device is reduced by placing the channel layer on the top of the triangular void. The formation of the triangular void is well characterized by both the growth parameters of the SMOCVD and the mask orientation. The maximum extrinsic transconductance of 260 mS/mm is obtained for the gate length larger than 2 µm and the measured source resistance is 0.25 Ω·mm. It is also observed that the measured transconductance is almost independent of the gate length when the fabricated gate has a length between 2.0 µm and 4.0 µm. The effective channel length is mainly determined by the short distance between two n+ layers for source and drain rather than the gate length. This device structure is suitable for low noise FET and for the simple realization of direct coupled FET logic inverter.

Neutron and proton irradiation of shallow channel GaAs direct-coupled field-effect-transistor logic devices and circuits

Neutron and proton irradiations have been performed on self-aligned GaAs metal-semiconductor field-effect transistors (MESFETs) and resistors utilizing shallow ion-implanted channels. FET threshold voltage shifts during irradiation were lower than reported elsewhere (less than 115 mV for a −0.85 V threshold FET irradiated by 4.3×1014 neutron cm−2). This is shown to be explained by the shallow active layers used. A neutron carrier removal rate between 20 and 25 cm−1 is necessary to fit the FET data. Carrier removal rates derived from resistor damage were 150 cm−1 for peak doping levels of 4×1017 cm−3, greatly in excess of those derived from epitaxial or bulk GaAs resistors, and inconsistent with values obtained from threshold shifts of FETs with identical active layers. Resistor and FET threshold voltage changes for 52 MeV proton irradiation were nearly an order of magnitude greater than for an equivalent dose of 1 MeV (Si) neutrons. The extrapolated worst-case failure dose of direct-coupled FET logic inverters was better than 1.8×1015 neutron cm−2 despite the limited noise margins of this logic scheme.

Characteristics of GaAs DCFL MESFET's and inverters exposed to high-energy neutrons

A systematic investigation of the effects of high-energy neutrons on GaAs metal-semiconductor field-effect transistors (MESFETs) and direct-coupled FET logic (DCFL) gates has been carried out. Measurements were made of the threshold voltage shifts and the transconductance and saturation current degradation of GaAs enhancement- and depletion-mode MESFETs, which comprise the DCFL logic gates, at neutron fluences ranging from 5*10/sup 13/-2*10/sub 15/ n/cm/sup 2/ (E>keV). DCFL inverter characteristics were measured and successfully simulated with SPICE using device parameters extracted from the neutron-damaged FETs. Ring oscillator measurements were made to determine the effects of high-energy neutrons on the frequency performance of DCFL circuits. Measurements confirm that propagation delays scale inversely with the device transconductance. The results of this investigation are useful in predicting how GaAs ICs, fabricated using DCFL logic, will perform in a high-energy-neutron environment. >