Leakage Current Of Diodes Research Articles

Silicon ultrafast recovery diode with leakage current reduced via the combined lifetime process of gold diffusion and electron-beam irradiation

We investigated the reduction in the reverse-biased leakage current of Si ultrafast recovery diodes via a combined lifetime process involving Au diffusion and bulk electron-beam irradiation (EI). The leakage current of the combined-processed diode was significantly reduced to less than one-third of that of the diode processed solely with Au diffusion, maintaining a similar switching time of 32 ns. This reduction was not achievable with the sole use of EI. Deep-level transient spectroscopy revealed that the reduction in the leakage current was due to the coexistence of the deep trap level of Au (E c-0.51 eV) and the shallow trap level of the defects (E c-0.39 eV) generated via EI as lifetime killers. By combining the deep and shallow trap levels, the lifetime of the carriers generated in the depletion layer of the reverse-biased p-n junction becomes long and consequently, the leakage current is reduced. By maintaining the trap density ratio of defects to diffused Au above 0.28, the leakage current was reduced to less than one-third of that in the solely Au-diffused diode, while maintaining a similar switching time.

Analysis of surface morphology at leakage current sources on large-area GaN-based p-i-n diodes

This paper investigated the relationship between the leakage current of GaN-based diodes with the large size of 8 × 8 mm2 under reverse bias and their responsivity, and it was found that reducing leakage current is an important way to improve the conversion efficiency of diodes. Leakage analysis was performed separately for two sizes of diodes. The location of the leakage was found by emission microscope, and the morphology of the leakage point was analyzed using a focused ion beam and a scanning electron microscope. It was found that structural defects, which may be caused by dropping substances during material growth, can form large leakage channels.

A 79 pW, 106 ppm/°C NMOS-only current reference with leakage current isolation based on body bias technique

A pico-watt, NMOS-only current reference has been proposed and simulated using 0.18-μm deep N-well CMOS process in this paper. To significantly reduce the power consumption to 79 pW and minimal operating voltage to 0.8 V, body bias technique is introduced. A level shift is proposed and used for isolating the N-channel/P-sub diode leakage current, which decrease the temperature coefficient to 106 ppm/°C when temperature changes from 0 to 125 °C. Besides, the line sensitivity and line regulation are obtained as 1.39%/V and 0.31%/V, respectively.

Interface engineering of p-type quaternary metal oxide semiconductor interlayer-embedded β-Ga2O3 Schottky barrier diode

Here, we propose a p-type copper aluminum oxide (p-CuAlO2) interlayer for the high breakdown and low leakage current of β-Ga2O3 Schottky barrier diodes (SBDs). The XPS and TEM analysis was employed to confirm the surface elemental compositions, chemical states, and microstructural properties of RF sputtered p-CuAlO2 thin films on β-Ga2O3. The electrical and carrier transport properties of Pt/β-Ga2O3 SBD and Pt/p-CuAlO2/β-Ga2O3 heterojunction (HJ) were studied by using current-voltage (I–V) and capacitance-voltage (C–V) measurements. In comparison to the SBD, the HJ displayed superior rectifying behavior, lower reverse leakage current, lower on-resistance, and a larger turn-on voltage. Higher barrier height (BH) was attained for the HJ compared to the SBD, which enabled the p-CuAlO2 interlayer to alter the barrier height. The reverse breakdown voltage of HJ increased by nearly 300 V compared to SBD and reached a maximum of 922 V. The BH values were extracted from the I–V, Hernandez, Cheung's, Mikhelashvili, Norde's, Chot, and surface potential methods found the values are comparable with one another, which indicates their steadiness and validity. The energy distribution profile of the interface state density (NSS) of the HJ decreases compared to the SBD, which indicates that the p-CuAlO2 interlayer facilitated the reduction of NSS of the Pt/β-Ga2O3 SBD interface. The forward log(I)-log(V) plot of the SBD and HJ reveals the ohmic nature at low voltage regions and space-charge limited conduction at higher voltage regions. Results reveal that the reverse leakage current conduction mechanism of the SBD and HJ showed that the Poole-Frenkel conduction mechanism is found to be governed in the lower voltage region, whereas the Schottky conduction mechanism is found to be directed in the higher voltage region, respectively. These outcomes point out that the p-CuAlO2 is a high potential candidate material for forming a heterojunction with β-Ga2O3.

Electrical properties of Cu/Pd2Si Schottky contacts to AlGaN/GaN-on-Si HEMT heterostructures

In this study, we analyze gold-free Cu/Pd2Si Schottky contacts to AlGaN/GaN-on-Si HEMT (high electron mobility transistor) heterostructures. The silicide layers are fabricated through magnetron sputtering deposition using a stoichiometric Pd2Si target and are subjected to post-gate annealing at different temperatures. After annealing at 500 °C the leakage currents of the planar diodes are reduced below 3.2 mA/cm2. The microstructures of the diodes are analyzed through transmission electron microscopy (TEM). The post-gate annealing increases lateral dimensions of silicide grains. The electrical properties of the contacts are determined by performing temperature-dependent current-voltage (I-V-T) measurements. The forward current exhibits a specific voltage dependence, which is interpreted based on the two-diode model, reflecting the properties of the Pd2Si/heterostructure interface along with those of the heterostructure itself. The model is fitted to extract the parameters of the Schottky contacts. The barrier height of 0.91 eV and ideality factor n = 1.5 are obtained after post-gate annealing at 500 °C. The effects of post-gate annealing on the forward conduction and leakage mechanisms are then discussed. A simple method is proposed to estimate the polarization charge density, which is required to calculate the electric fields in the heterostructure in the reverse bias. It is observed that post-gate annealing affects the I-V characteristics, likely by reducing the density of the unintentional donors and trap states, leading to an increase in the apparent barrier height along with a reduction in the density of defects contributing to the leakage current.

Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator

A tiny-size ultra-low voltage CMOS voltage reference operating at quiescent picoamp scale has been proposed in this paper to fit the high standards of modern wireless microsystems. Without any on-chip resistor or operational amplifier (opamp), the sensitive core of the proposed voltage reference is protected from the glitches of the power supply via a temperature-dependent cascode current source biased by the output. The upper limit of the output temperature range is broadened by the increased diode leakage current of the proposed current generator. The case study deals with implementation of the new circuit and post-layout simulation results in 0.18-μm CMOS technology. The circuit occupies an active area of 629 μm2, consuming almost 690 pA from 0.3 V minimum supply voltage at room temperature. The untrimmed 229 mV output voltage exhibits an average temperature coefficient (TC) of 47.39 ppm/°C over the −40 °C–140 °C temperature range. The line-voltage sensitivity (LS) is 0.17%/V when the input supply is varied from 0.3 V to 1.8 V, and can be improved by 9 × if the lower limit of the power supply is increased to 0.4 V. The DC power supply ripple rejection (PSRR) is lower than −80 dB for the line voltage beyond 0.5 V.

Mechanism of Reverse Leakage Current in Schottky Diode Fabricated on Large Bandgap Semiconductors like Ga2O3 or Diamond Part II

The bandgap of Ga2O3 (4.5-4.9 eV) is larger than the bandgap of GaN (3.4 eV). In addition, single crystal bulk Ga2O3 wafers can be more easily manufactured than GaN wafers. Therefore, Ga2O3 has strong potential for applications in high power semiconductor devices [1]. Schottky diodes fabricated on n-type Ga2O3 have strong potential as fast high-power switching devices. Similarly, the bandgap of diamond (5.5 eV) is very large and diamond Schottky diodes have good potential.One possible mechanism of reverse leakage current in Schottky diodes is image force barrier lowering at the metal-semiconductor interface. Historically, there were 2 theories regarding the image force barrier lowering effect. In 1953, Krömer published his theory that the image force dielectric constant in the equation for Schottky emission should be equal to 1 [2]. Subsequently in 1964, Sze et al. published their theory that the image force dielectric constant in the equation for Schottky emission should be equal to n2 [3], where n is the refractive index of the semiconductor in the infrared or visible light range. In 1969, Sze published a book which has influenced many scientists [4]. Sze’s theory [3]-[4] quickly became the dominating theory whereas Krömer’s theory essentially became a forgotten theory. In 2020, the author pointed out that Krömer’s theory is quite frequently more compatible with experimental results for Ga2O3 or diamond Schottky diodes [5]. In 2021, the author attempted to propose a new theory involving the concept of electron velocity overshoot to unify Krömer’s theory and Sze’s theory, as shown in Fig. 1 [6]; Krömer’s theory is better than Sze’s theory for high reverse bias voltage.In conclusion, the author pointed out that it is necessary to resurrect an old and forgotten theory from Krömer in order to explain the experimental data on the reverse leakage current of Schottky diodes fabricated on large bandgap semiconductors like Ga2O3 and diamond, etc. A theoretical basis based on quasi-ballistic transport will be provided.

Schottky Barrier Characteristic Analysis on 4H-SiC Schottky Barrier Diodes With Heavy Ion-Induced Degradation

Leakage current of 1200-V 4H-SiC Schottky barrier diodes (SBDs) with different structures increased by various degrees after heavy-ion exposure. By taking <inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> measurements in a range of 298 to 448 K, the voltage dependence of saturation current (<inline-formula> <tex-math notation="LaTeX">$I_{0}$ </tex-math></inline-formula>), barrier height (<inline-formula> <tex-math notation="LaTeX">$\phi _{B0}$ </tex-math></inline-formula>), and ideality factor (<inline-formula> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula>) were obtained. The dependence of these parameters with temperature illustrates the Gaussian distribution of barrier height. The inhomogeneity of the Schottky barrier height (SBH) distribution was successfully described using a modified thermionic emission (TE) model with Gaussian distribution, and the average barrier height (<inline-formula> <tex-math notation="LaTeX">$\bar {\phi }_{B0}$ </tex-math></inline-formula>) was gained. The results show that the barrier height distribution of all SBDs remain unchanged after the irradiation which means heavy-ion exposure did not affect the Schottky barrier.

Effects of Fermi pinning and quantum mechanisms on leakage current of 4H-SiC Schottky diodes

Reverse bias leakage current through 4H-SiC Schottky diodes was modeled using quantum transmission theory and the theoretically calculated values were compared with the measured values from fabricated Schottky diodes. To account for interface defects, energy barriers due to Fermi pinning from previously observed defects were used in place of the ideal barrier structure predicted by the Schottky–Mott rule. Incorporating barriers with energy values set due to Fermi pinning at known defect energies resulted in better experimental agreement by many orders of magnitude.

Investigation on the leakage current characteristics of large size GaN diodes

The leakage mechanism of large size GaN p–i–n diodes is studied, and the possible reasons are analyzed. It is found that (i) the leakage current of most diode chips is not proportional to their area, and the leakage problem deteriorates seriously when the size of the device increases; (ii) the open circuit voltage of the photovoltaic device decreases with the increasing leakage current of GaN diodes; and (iii) low density nanotubes are detected in larger size GaN diodes, which is one of the important reasons for the large leakage of large size GaN diodes.

Halide Perovskite Precursors Dope PEDOT:PSS

AbstractHalide perovskite semiconductors find use in a broad range of optoelectronic applications including photovoltaic solar cells and light‐emitting diodes. In such devices the semiconductor is sandwiched in between interlayers for charge transport, extraction, or injection. When it comes to hole transport layers, the conducting polymer PEDOT:PSS has become an ubiquitous material. The halide perovskite thin film is commonly obtained by crystallization of precursors using solution processing on top of PEDOT:PSS. It is demonstrated here that such a widely spread technique is actually affecting the electrical properties of the underlying conducting polymer. The halide perovskite layer and precursors are drastically doping the PEDOT:PSS, its conductivity being increased by two orders of magnitude from 0.2 to 20 S cm−1. The depth of penetration of halide dopants is determined to be higher than 150 nm, superior to the usual thickness of PEDOT:PSS films. This phenomenon has important impact on diode leakage currents, on emission patterns of perovskite LEDs and on overestimated photocurrent density in perovskite solar cells embedding the PEDOT:PSS interlayer.

A 17.5dB wide-dynamic range high-efficiency RF-to-DC power converter for wireless energy harvesting

ABSTRACT A novel reconfigurable RF-to-DC power converter is proposed for wireless energy harvesting. The proposed RF rectifier employs low-threshold transistors with cross-coupled configuration to enhance the flow of the forward current to the load at low input RF power and adaptive stacking diodes to reduce the leakage current by lowering the driving voltage of the rectifying PMOS transistors at high input RF power. The proposed rectifier utilises the body biasing technique to modulate the threshold voltage and minimises the leakage current of the feedback diodes. The proposed novel techniques improve efficiency and extend the dynamic range. The prototype is implemented in a 65 nm CMOS technology and occupies an active area of 0.0148 mm2. The proposed rectifier achieves a peak power conversion efficiency (PCE) of 76% with a load of a 100-KΩ load at the industrial, scientific, and medical band 433 MHz, and the achieved sensitivity of the rectifier is −18.5 dBm for 1 V DC output voltage. The proposed rectifier offers PCE at −35 dBm of 45.6%, which is the best low-power performance. Compared to the state-of-the-art rectifiers, the proposed design achieves an excellent wide-dynamic range of 17.5 dB, which is ten times better than the conventional cross-coupled rectifier.

(Invited) Defect Engineering for Monolithic Integration of III-V Semiconductors on Silicon Substrates

Implementation of high-mobility channel materials enables to increase the device performance due to the higher carrier mobility compared to silicon devices. III-V based materials such as GaAs and ternary systems (e.g. InxGa1-xAs alloys) are achieving high performing n-channel transistors. The strong progress in hetero-epitaxy using nano ridge engineering [1] leading to monolithic heterogeneous integration of III-V materials on silicon substrates resulted in state-of-the-art FinFETs, gate-all-around (GAA) and horizontal or vertical stacked nanowires (NW) on 300 mm Si wafers [2,3]. Very promising results have also been reported for GaN on Si triggering their use for high power and RF applications [4].One of the main challenges remains a good defect control in order not to degrade the electrical performance of devices and circuits [5]. The nucleation of extended defects is directly related to the hetero-epitaxial growth of layers with a lattice mismatch and their concentration depends on the composition of the layers such as e.g. the In content in InxGa1-xAs and the Al content in AlxGa1-xN. The defects have a direct impact on the generation and recombination lifetime and the leakage current [5], while also the low frequency noise (LFN) performance is influenced [6]. The identification of the defects (energy level ET, capture cross section and concentration) can be determined using Deep Level Transient Spectroscopy (DLTS) and low frequency noise spectroscopy by measuring LFN as a function of temperature.The goal of this work is to review the knowledge about defect engineering and to analyze the electrical activity of extended defects in III-V semiconductors on silicon substrates. Different case studies will be used to illustrate both the defect identification and the electrical activity of the defects. The impact of the used processing schemes to fabricate the devices is also discussed. It will e.g. be shown that defects in GaN/AlGaN MOSHEMTs increase the low frequency noise due to generation-recombination centers in the GaN depletion layer [7]. These traps can lead to a distortion of the current-voltage characteristics of short channel devices. DLTS studies are a powerful tool to identify traps and to investigate their impact on the leakage current of III-V on Si devices. Double correlation DLTS investigations on GaAs/InGaP/GaAs diodes pointed out that traps associated with sidewall interface states can dominate the peripheral diode leakage current. The focus of the presentation will be on the current understanding of defect engineering associated with the monolithic integration of III-V materials on Si and a discussion of recent results concerning the electrical activity of the defects and the defect modeling.[1] M. Baryshnikova et al., Crystals, 10, 330 (2020).[2] X. Sun et al., Digest VLSI Technology, T3-4 (2017).[3] A.P. Milemin et al., Microelectron. Eng., 192, 14 (2019).[4] L. Li et al., IEEE Electron Device Lett., 41, 689 (2020).[5] C. Claeys et al., ECS Solid State Electronics, 9, 03301 (2020).[6] C. Claeys et al., J. Phys. Cond. Ser., 1190, 012001 (2019).[7] K. Takakura et al., IEEE Trans. Electron Dev., 67, 3062 (2020).

A CMOS Adaptive 433/900 MHz Differential RF Power Harvester with Wide-Dynamic Range for Wireless Powering

A wide-dynamic range high-efficiency differential RF-to-DC power converter for wireless power transfer (WPT) applications is presented. The architecture offers high power conversion efficiency (PCE) over a wide range of input powers by employing cross-coupled high-threshold rectifying devices with stacking diodes. The proposed rectifier uses the adaptive biasing technique to control the rectifying devices’ conduction and minimizes the leakage current of the feedback diodes by utilizing the dynamic body biasing. Compared to the conventional cross-coupled rectifier, the proposed rectifier has a [Formula: see text] dynamic range. A prototype of the proposed rectifier is implemented in 65-nm CMOS technology and occupies an area of 0.0148[Formula: see text]mm2. The rectifier achieves [Formula: see text][Formula: see text]dBm sensitivity for 1[Formula: see text]V output and a 79.4% peak PCE. A dynamic range of 17.3[Formula: see text]dB is achieved at the 433[Formula: see text]MHz in the Industrial Scientific Medical band (ISM band) with a 100-K[Formula: see text] load. Furthermore, the proposed design offers a peak PCE of 62.6% and a wide dynamic range of 16.1[Formula: see text]dB at the UHF 900[Formula: see text]MHz band with a load resistance of 100-K[Formula: see text].

Parasitic p–n junctions formed at V-pit defects in p-GaN

The luminescent and recombination properties of V-pit defects in p-GaN(Mg) grown by metalorganic chemical vapor deposition (MOCVD) were studied by scanning electron microscopy (SEM) in the secondary electron, cathodoluminescence (CL), and electron beam induced current (EBIC) modes, combined with CL spectra measurements and EBIC collection efficiency measurements. Similar studies were performed on low-dislocation-density freestanding n-GaN crystals. For MOCVD p-GaN films, the SEM investigations were supplemented by capacitance–voltage, current–voltage, deep level transient spectroscopy analysis with Ni Schottky diode, and Ohmic contacts. These experiments show that V-pits in p-GaN increase the leakage current of Schottky diodes, as in n-GaN films and crystals. EBIC imaging and EBIC collection efficiency results suggest that in the region of V-pits, a parasitic p–n junction is formed. We also observe that, in V-pits, the CL spectra the contribution of the 3.2 eV defect band is strongly enhanced compared to the 3 eV blue CL band that dominates the spectra.

Influence of the DLC Passivation Conductivity on the Performance of Silicon High-Power Diodes Over an Extended Temperature Range

The diamond-like carbon (DLC) is important for passivation of junction termination in high power devices due to its excellent electrical, mechanical, and thermal properties. While the role of conductivity and polarization of the DLC layer on the blocking capability of a p-n junction has been explained recently, the thermal behavior still needs to be addressed. For this purpose, the diode leakage current was measured on large area power diodes with negative bevel coated by the DLC in a typical industrial range between 300 and 413 K. An unusual deviation from the expected Arrhenius law was experimentally observed. A predictive TCAD model, which incorporates the effect of the DLC layer, has been developed to study the impact of the DLC layer parameters on diode thermal performance. Both the electrostatic features and charge transport mechanisms through and along the DLC/Silicon interface have been modeled over a wide range of temperatures. Different DLC/Silicon doping combinations have been analyzed to explain the main effects determining the temperature dependence of diode leakage current and breakdown voltage. A complete validation of the TCAD approach has been achieved.

Application of p-type NiO deposited by magnetron reactive sputtering on GaN vertical diodes

In this study, p-NiO deposited by magnetron reactive sputtering was adopted to fabricate NiO/GaN heterojunction and edge termination structure for vertical GaN Schottky barrier diodes. The contact properties of the NiO/GaN heterojunction were evaluated through a vertical pn diode. Turn-on voltage and specific on-resistance are approximately 2.27 V and 1.42 mΩ cm2, respectively. Temperature-dependent current-voltage and low-frequency noise measurements confirm that good interface and thermal stability of NiO/GaN heterojunction are obtained. The leakage current of the NiO pn diode is approximately four orders of magnitude lower than that of Schottky barrier diode, leading to an enhanced breakdown voltage. The p-NiO was selectively deposited as an edge termination structure to alleviate the electric field crowding of Schottky barrier diode, which is beneficial for enhancing the breakdown voltage.

Effect of the Field Oxidation Process on the Electrical Characteristics of 6500V 4H-SiC JBS Diodes

The effect of the field oxidation process on the electrical characteristics of 6500V 4H-SiC JBS diodes is studied. The oxide thickness and field plate length have an effect on the reverse breakdown voltage of the SiC JBS diode. According the simulation results, we choose the optimal thickness of the oxide layer and field plate length of the SiC JBS diode. Two different field oxide deposition processes, which are plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD), are compared in our paper. When the reverse voltage is 6600V, the reverse leakage current of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 0.7 μA, which is 60% lower than that of PECVD process. When the forward current is 25 A, the forward voltage of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 3.75 V, which is 10% higher than that of PECVD process. There should be a trade-off between the forward and reverse characteristics in the actual high power and high temperature applications.

(Invited) Nickel and Nickel-Platinum Silicide for BiCMOS Devices

Recently, the world’s fastest SiGe-HBT was presented by IHP researchers [1], which applies low ohmic nickel silicide (NiSi). Among other measures, this feature contributed to speed improvements. On the other hand, the integration of low-ohmic NiSi creates the risk for NiSi defects which could result in increased MOSFET leakage currents. The goal of this contribution is to find out from several two-step silicidations of Ni or NiPt layers a suitable process for a BiCMOS technology which enables low silicide RS for high cutoff frequencies of bipolar and MOS transistors without degradation of leakage currents. In result, a 300°C/450°C silicidation is proposed providing RS values of 3 to 4 Ω for both NiSi and NiPtSi. However, only the NiPtSi shows acceptable low leakage currents compared to NiSi. Therefore, NiPt extends the silicide process window for HBTs and MOSFETs.The phase transitions of Ni and NiPt silicides as a function of temperature are shown in Fig. 1, where the temperature range of the targeted NiSi phase is enlarged for NiPt compared to Ni. The investigated two-step NiSi formations are listed in Table 1. The NiPt layers were deposited in an Applied Materials laboratory. First, Ni2Si was formed by furnace anneal, low pressure anneals, or by a NiPt sputtering at 400°C. The Ni rich silicide was converted into NiSi by a second anneal at 450°C.The final Ni(Pt)Si sheet resistance (RS Ni(Pt)Si:1.+2.Ann) was tunable from 1.5 Ω to 10.5 Ω by the temperature and time of the first anneal (Fig. 2). At 300°C, the RS saturates at 3.3 Ω for 20 nm Ni and 1.6 Ω for 40 nm Ni, respectively. This indicates full Ni consumption. The furnace anneals at 200°C and 230°C do not show any RS saturation since Ni is consumed only partially. An RS increase for NiSi and NiPtSi on PSD (p source-drain) compared to NiSi on substrate is observed.One figure of merit of SiGe-HBTs is the maximum oscillation frequency fmax, which depends by the following equation fmax=sqrt(fT/(8πrBcBC)) on the transit frequency fT, the base resistance rB, and the collector-base capacitance cBC. A silicide resistance variation could mainly influence rB. In Fig. 3a, the sheet resistance of the silicided base polysilicon (RS BasePolySilicide) together with fmax of two HBT layouts are plotted for several silicide formations. It exists a correlation between fmax and RS BasePolySilicide, which is shown in Fig. 3b. In general, fmax could be enlarged by a silicide resistance reduction for special HBT layouts.For these low-ohmic and thick Ni(Pt)Si layers, special attention has to be paid to the MOSFET leakage currents, which can be enlarged by lateral silicide pipes towards the conducting channel or by defects along the SD – STI (shallow trench isolation) interface [2]. Another leakage current source are silicide spikes shortening in a perpendicular direction the SD and the well. Three types of P+Nwell and N+Pwell diodes are suitable to determine and distinguish these silicide based yield killers: area diodes to detect spikes, STI separated island diodes to recognize SD-STI defects, and diodes with long poly-gates on SD-well areas to determine pipes at gate edges. In result, the area and island diodes showed no leakage current increase for the studied silicidations, i.e. defects along the SD-STI edge and spikes are not critical here. The leakage currents of gate-edged diodes on N+Pwell and P+Nwell are presented in Fig.4. Both diode types show low leakage currents for the 200°C and 230°C anneals, because the low lateral silicidation at these temperatures reduces the probability for piping. At 300° the N+Pwell leakage current increases slightly up to 2x10-9A, but significantly up to 1x10-7A for the P+Nwell diode. This is a clear indication for pipes at the gate edges [3]. In contrast, almost no enhanced leakage current was observed for the NiPt silicidations with 200° to 300°C anneals. The pipe suppression of the NiPt silicide system might be caused by the Pt agglomeration at the silicide-SD interface [4]. The limits of the NiPt pipe suppression are shown for N+Pwell diodes silicidated with a NiPt deposition at 400°C. Leakage currents of 1x10-8A could indicate NMOS-typical pipes, as described by Yamaguchi [5].In summary, silicide layers with low RS values of 3Ω to 4Ω were formed by two-step annealing of Ni and NiPt at 300°C and 450°C. These silicides support high fmax values of SiGe HBTs. However, only the NiPt silicide process provided acceptable low leakage currents of MOSFET test structures indicating an extended process capability of NiPtSi compared to NiSi. Figure 1

Model Dye-Sensitized Solar Cell dan Aplikasinya Berdasarkan Data Temperatur Harian: Studi Kasus Pangkalpinang

&lt;p&gt;Dye-Sensitized Solar Cells (DSSC) is photovoltaic with a dye that functions as an acceptor of sunlight. The great potential of using DSSC lies in the ease of the synthesis process, and the dyes used can come from plants. However, like most other solar cells, increasing the operating temperature can degrade the DSSC performance and thus decrease the efficiency. This article presents a model of the relationship between the effect of temperature on DSSC performance. The model proposed is derived from the DSSC equivalence with a diode circuit. By confirming the experimental research results, it is known that the model presented in this study has excellent accuracy on various DSSC performance parameters (R2&amp;gt; 0.99). The performance studied includes the I-V curve's shape, the value of the short-circuit current, the diode leakage current, and the open-circuit voltage. Based on daily temperature data in Pangkalpinang City, the potential performance of the DSSC could also be determined when it was developed in Kep. Bangka Belitung. The short-circuit current value obtained is in the range of 14 A with a voltage of 0.6 V. It is hoped that this proposed model can be information for the development of DSSC because of its enormous potential application in Indonesia.&lt;/p&gt;