Digitally Controlled Oscillator Tuning Research Articles

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

This work presents a low-jitter and low out-of-band noise two-core fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital bang-bang phase-locked loop (PLL). Two novel techniques are introduced to efficiently suppress the quantization noise (QN) of the digitally controlled oscillator (DCO) and to achieve an optimal trade between power consumption and PLL noise. The digital period averaging technique, working in background of the main system, enables the use of a low-power XOR-based quadrupler for clocking <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator dithering the DCO tuning word. The true-in-phase combiner circuit implements a digitally assisted power combination of two PLL outputs, to optimally reduce the impact of the PLL noise sources. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.47 mm2 and synthesizes frequencies from 8.5 to 10.5 GHz while dissipating 36 mW. The measured rms jitter (integrated from 1 kHz to 100 MHz and including spurs) is 72 fs for near-integer channels, with a worst case fractional spur of −59.7 dBc, while the measured out-of-band noise is −140.7 dBc/Hz at a 10-MHz offset.

A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope

A 24 GHz self-calibrated all-digital frequency-modulated continuous-wave (FMCW) synthesizer is presented in this article. A multi-bank digitally controlled oscillator (DCO) is employed to provide adequate frequency tuning range and high frequency resolution. A full background self-calibration scheme is proposed to linearize the DCO tuning curve for highly linear and fast chirp generation. An overlap compensator based on an adaptive lookup table (LUT) is utilized to eliminate the frequency overlaps between adjacent DCO tuning bands. The compensation words in the LUT are altered by least-mean-square (LMS) algorithm for robust and precise matching. A ramp tracker, which features real-time ramp tracking with zero steady-state phase error, is employed to estimate and stabilize the frequency ramp. Implemented in 40 nm bulk CMOS, the FMCW synthesizer prototype consumes 28 mW with a 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. The maximum chirp bandwidth is 3.2 GHz, corresponding to 13.33% of the center frequency. Measurement results show that the root-mean-square (RMS) frequency error is reduced by 1/10 with self-calibration after 2 ms convergence time. The maximum chirp slope is up to 320 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> with 309 kHz RMS frequency error. The minimum RMS frequency error is 7.35 kHz under 5 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> chirp slope, corresponding to 0.0002% of the chirp bandwidth.

Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

A 67-fsrms Jitter, −130 dBc/Hz In-Band Phase Noise, −256-dB FoM Reference Oversampling Digital PLL With Proportional Path Timing Control

An LC oscillator-based reference oversampling PLL (OSPLL) is proposed in this work. An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28-nm CMOS process, the proposed PLL achieves 67.1-fs RMS-jitter with 5.2-mW power consumption, which translates to −256-dB FoM. The in-band phase noise of the PLL is −130 dBc/Hz at 4-GHz output frequency. The reference spur of the proposed PLL is −78 dBc.

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.

A Small-Area Solenoid Inductor Based Digitally Controlled Oscillator

This paper presents a wide band, fineresolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 ㎛ digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 ㎛ process and the die area of the solenoid inductor is 0.013 ㎟. The DCO tuning range is about 54 % at 4.1 ㎓, and the power consumption is 6.6 ㎽ from a 1.2 V supply voltage. An effective frequency resolution is 0.14 ㎑. The measured phase noise of the DCO output at 5.195 ㎓ is -110.61 ㏈c/㎐ at 1 ㎒ offset.

A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 μm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 μm process and the die area of the solenoid inductor is 0.013 mm2. The DCO tuning range is about 52 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is Â?110.17 dBc/Hz at 1 MHz offset.

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking; and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The proposed proportional path decouples the detector quantization error and oscillator noise bandwidth tradeoff and helps maximize bandwidth to suppress digitally controlled oscillator (DCO) phase noise in a power efficient manner. A double integral path alleviates the tradeoff between DCO tuning range and its frequency quantization error. The high resolution of the DCO was maintained over a wide range of sampling clock frequencies by using a delta-sigma digital to analog converter and a continuously tunable switched-RC filter. Bandwidth and tuning range tracking are employed to achieve low jitter over the entire operating range. The prototype DPLL, fabricated in a 90 nm CMOS process, operates from 0.7 GHz to 3.5 GHz. At 2.5 GHz, the proposed DPLL consumes only 1.6 mW power from a 1 V supply and achieves 1.6 ps and 11.6 ps of long-term r.m.s and peak jitter, respectively.

Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC

In this paper, we propose a low-power all-digital phase- locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm2 using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

Wide-Band Fine-Resolution DCO with an Active Inductor and Three-Step Coarse Tuning Loop

This paper presents a wide-band fine-resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three-step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.

Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting

Design of a fast-locking phase-locked loop (PLL) is one of the major challenges in today&apos;s wireless communications. A recently reported digitally controlled oscillator (DCO)-based all-digital PLL (ADPLL) can achieve an ultrashort settling time of 10 µs. This study describes a new DCO tuning word (OTW) presetting technique for the ADPLL to further reduce its settling time. Estimating the required OTW is the most crucial issue for presetting. Two methods are proposed here to estimate the required OTW. One method is using a foreground calibration block to eliminate the effect of DCO gain (KDCO) estimation error (ɛK) and then directly calculating the required OTW for the process/voltage/temperature calibration (PVT-calibration) mode of the ADPLL. The other method is using a new counter-based mode switching controller (CB-MSC) to estimate the required OTW for the acquisition mode and tracking mode. This method is based on the ADPLL&apos;s inherent characteristic of frequency toggling and is independent of loop parameters. Furthermore, our proposed presetting technique can be used with the dynamic loop bandwidth control technique together. The ADPLL with the proposed OTW estimating and presetting block is designed using very-high-speed integrated circuit hardware description language and simulated in ModelSim environment. Simulation results demonstrate that a minimum settling time of 2.9 µs is achieved and the improvement is about 40–50% on average compared with the ADPLL without our techniques.