Design Of Digital VLSI Circuits Research Articles

Fusion of powerful features of Harris Hawks with Cuckoo Search algorithm for engineering applications

The High-level synthesis (HLS) is a key step in the digital VLSI circuit design. HLS can be seen in the present study as an important matter of intelligently map a Data Flow Graph (DFG) specification of digital filters to FPGA. In this article, the powerful features of the Harris hawks optimization (HHO) and Cuckoo search (CS) algorithm have improved the performance of the proposed method. This proposed strategy is also known as the GChO algorithm. In GChO, the phase of CS helps to force the HHO to escape from stagnation, to ignore local optima and premature convergence. In addition for HLS, the three retiming-based models were also proposed in the work. The standard pipelining was employed in Model 1. The modified Min-Period Retiming on the multiplier less digital filters was incorporated by Model 2 and led to a significant improvement in clock frequency. Model 3 adopted modified Min-Area Retiming on digital filters and reduced the complexity of the circuit; however these designs therefore offer single parameter-based heuristic solution. This can be resolved by using meta-heuristic approach focused on retiming. The use of meta-heuristic methods and swarm intelligence has been considered as a highly desirable choice when searching the digital block solution space with higher frequency and reduced complexity in HLS problems. The robustness of the GChO method has been verified on IEEE CEC’ 2020 standard benchmark test suites. The paper analyzes that the performance of the proposed GChO algorithm outperforms the Harris hawks optimization (HHO), Moth Flame optimization algorithm, Particle Swarm optimization algorithm, Chimp optimization algorithm for the HLS digital filters. The experimental results show that the proposed Model 2 and 3 for retimed PDR-FIR filter is improved in term of MUF by 7.38% and utilized slices by 37.77%, PRO-DFII IIR retimed filter by 10.54%, and complexity reduced by 29.69%, PRO-LAT-ARF by 41.61% and slice by 11.17% and PRO-LATLAD-IIR improved in term of MUF, slices by 35.69% and 38.095% in relative to the standard retimed filters of various architecture. For the evolutionary GChO-retimed filter, an improvement in MUF by 58.52%, and utilized slices by 49.61%, for PDR-FIR, 48.09%, 80.76% for PRO-DFII-IIR , 52.68%, 54.33% for PRO-LAT-ARF, 27.85% and 18.46% for PRO-LATLAD-IIR are achieved in respect of Model 2 and 3 whereas an improvement in term of MUF by 34.60%, and utilized slices by 37.61%, for PDR-FIR, 40.55%, 39.66% for PRO-DFII-IIR, 40.08%, 31.33% for PRO-LAT-ARF, 26.95%, 24.41% for PRO-LATLAD-IIR are achieved with respect of other meta-heuristic methods.

Implementation of Energy Effective Error Resistant Adders and Multipliers in Image Denoising Applications

The design of digital VLSI circuits must take energy efficiency into consideration. Reducing the circuit’s power consumption, which has been a major issue since 2000, would increase the necessity for energy efficiency. Error-tolerant systems heavily rely on approximate computation methods to increase power efficiency. The key factors of the system’s overall power consumption and area computation are adders and multipliers, which are also crucial in approximate computing. High energy-efficiency adders can be used to create additional multipliers. In order to dramatically minimize power consumption, this work builds and implements 8×8 Dadda multipliers using 1 bit approximation adders. Calculation is sped up by using the Dadda multiplier. In turn, by reducing propagation latency, the suggested design lowers power consumption in digital CMOS circuitry. The proposed multiplier design with approximate adders, which was created in Verilog HDL, simulated in FPGA, and synthesized in FPGA platform, is implemented on an ASIC platform using Cadence 90 nm Technology. The Gaussian filter additionally employs the proposed Dadda multiplier for picture denoising in approximation adder-based image processing applications.

A novel method for high-level synthesis of datapaths in digital filters using a moth-flame optimization algorithm

High-level synthesis (HLS) is one of the most important processes in digital VLSI circuit design. Owing to complexity and enormity of the design space in HLS problems, employing meta-heuristic methods and swarm intelligence has been considered as a highly favorable option when solving such problems. This research work proposes a moth-flame optimization (MFO) algorithm-based method for HLS of datapaths in digital filters, where scheduling, allocating, and binding steps were performed simultaneously. It was observed that the efficiency of the proposed method enjoyed an improved efficiency thanks to the mentioned simultaneous steps while being combined with the MFO algorithm. By comparing the performance of the proposed method with Genetic algorithm based method and particle swarm optimization based method for HLS of digital filters benchmarks, it can be inferred that the proposed method outperforms the other two methods in HLS of digital filters. This is evidently approved by a maximum improvement observed in the rates of the delay, the occupied area of the chip, and the power consumption for 2.99%, 6.58%, and 6.48%, respectively. In addition to the mentioned improvement, another striking characteristic of the proposed method is its fast runtime in reaching a response. This could significantly lower the costs while increasing the design speed of circuits having large dimensions. As well, an averagely 20% rise was also discerned in the algorithm runtime compared to the other two methods.

High performance full subtractor using floating-gate MOSFET

Low power consumption has become one of the primary requirements in the design of digital VLSI circuits in recent years. With scaling down of device dimensions, the supply voltage also needs to be scaled down for reliable operation. The speed of conventional digital integrated circuits is degrading on reducing the supply voltage for a given technology. Moreover, the threshold voltage of MOSFET does not scale down proportionally with its dimensions, thus putting a limitation on its suitability for low voltage operation. Therefore, there is a need to explore new methodology for the design of digital circuits well suited for low voltage operation and low power consumption. Floating-gate MOS (FGMOS) technology is one of the design techniques with its attractive features of reduced circuit complexity and threshold voltage programmability. It can be operated below the conventional threshold voltage of MOSFET leading to wider output signal swing at low supply voltage and dissipates less power as compared to CMOS circuits without much compromise on the device performance. This paper presents the design of full subtractor using FGMOS technique whose performance has been compared with full subtractor circuits employing CMOS, transmission gates (TG), complementary pass transistor logic (CPL) and gate diffusion input (GDI). It has been observed that the FGMOS based full subtractor uses minimum number of transistors (10) while consuming least power (1.61×10−9W) with lowest propagation delay (10.62ps) and power delay product (0.17×10−19Js) besides occupying minimum surface area (0.25×10−7cm2) in comparison to CMOS, TG, CPL and GDI based full subtractors available in literature, thus suitable for swift miniaturized applications.

Design error diagnosis and correction via test vector simulation

With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits.

Digital VLSI circuit design and simulation of an adaptive resonance theory neural network

A digital VLSI circuit design for an adaptive resonance theory (ART) neural network architecture, called the augmented ART-1 neural network (AARTI-NN) is presented. An ‘axon-synapse-tree’ structure is used to realize the activities of the short-term memories and reset subsystem. The long-term memory traces are implemented using NMOS transmission gales. PSpice circuit simulation was carried out to verify the design of a prototype, seven-node AARTI-NN. A clock-controlled delay element is included in the simulation to illustrate the functionality of the AARTI-NN. It is shown that the AARTI-NN node selection activities simulated from the circuit designed are identical to those described by the coupled differential equations governing the AARTI-NN.