Digital VLSI Chip Research Articles

Design of thermally aware ultra low power clock generator for moderate speed VLSI chip applications

ABSTRACTSub-threshold operation of devices provides a promising approach to satisfy the ultra-low power demand of handheld products. However, in this domain, the drive current exponentially depends on temperature which makes the sub-threshold circuits more prone to temperature variations. This paper proposes a scheme to improve the thermal stability of an ultra low power clock generator circuit which is vital for reliable operation of portable synchronous digital VLSI chip applications. In this work, combination of temperature monitoring circuit and control circuit has been incorporated to develop a thermally robust clock generator. A novel control strategy is developed, wherein the control voltage is adaptively altered to combat the exponential change in the clock period with the variation in temperature, without use of any passive components like resistors and capacitors. Simulation results shows that the proposed circuit gives constant clock period against a wide range of temperature variations. The proposed oscillator operates at 0.37V, consumes 1.5µW power and provides a temperature coefficient of 290ppm/°C over a temperature range from 10°C to120°C without any external trimming.

Chip for linearisation of RF power amplifiers using digital predistortion

A digital VLSI chip is presented that implements the most critical part of a predistortion system for linearisation of RF power amplifiers. Measurements have shown that the chip provides seven times higher modulation bandwidth (208 kHz) at 10% power (100 mW) compared with a standard digital signal processor.

High-performance digital color video camera

Typical one-chip color cameras use analog video processing circuits. An improved digital camera architecture has been developed using a dual-slope AID conversion technique and two full-custom CMOS digital video processing integrated circuits, the color filter array (CFA) processor and the ROB postprocessor. The system uses a 768 x 484 active element interline transfer CCD with a new field-staggered 3G color filter pattern and a lenslet overlay, which doubles the sensitivity of the camera. The industrial-quality digital camera design offers improved image quality, reliability, and manufacturability, while meeting aggressive size, power, and cost constraints. The CFA processor digital VLSI chip includes color filter interpolation processing, an optical black clamp, defect correction, white balance, and gain control. The RGB postprocessor digital integrated circuit includes a color correction matrix, gamma correction, two-dimensional edge enhancement, and circuits to control the black balance, lens aperture, and focus.