Digital TV Tuner Research Articles

A Widely Tunable Bandpass CMOS Filter Based on a Low-Voltage Active Inductor

A Chebyshev bandpass filter for digital TV (DTV) tuner ICs, as an RF tracking filter, based on a low-voltage tunable active inductor (TAI) is presented. The new filter has a tuning range of 200–800[Formula: see text]MHz. Independent tuning of the inductance and central frequency of the filter are very important in this wide frequency span. Adjusting the inductance for tuning of the filter should not vary its quality factor and consequently performance of the filter. Use of a feedback resistor in the active inductor makes the inductance and quality factor tuning-independent. Moreover, the feedback resistor increases the quality factor of the active inductor. Biasing the bulk terminals of the devices to a positive voltage, we achieve low threshold devices and consequently low voltage TAI. The proposed filter has IIP3 and noise figure of [Formula: see text]0.8 to 9.5[Formula: see text]dBm and 19.1 to 20.9[Formula: see text]dB, respectively. Besides, the power consumption varies from 9.6 to 25.5[Formula: see text]mW in the tuning range of 200–800[Formula: see text]MHz.

A UHF CMOS Variable Gain LNA with Wideband Input Impedance Matching and GSM Interoperability

A UHF CMOS variable gain low-noise amplifier (LNA) is designed for mobile digital TV tuners. The proposed LNA adopts a feedback topology to cover a wide frequency range from 474 to 868 MHz, and it supports the notch filter function for the interoperability with the GSM terminal. In order to handle harmonic distortion by strong interferers, the gain of the proposed LNA is step-controlled while keeping almost the same input impedance. The proposed LNA is implemented in a 0.11 mm CMOS process and consumes 6 mA at a 1.5 V supply voltage. In the measurement, it shows the power gain of greater than 16 dB, NF of less than 1.7 dB, and IIP3 of greater than -1.7 dBm for the UHF band.

A highly linear low-pass Gm–C filter with a self-biasing transconductor for a digital TV tuner

To improve the linearity of the transconductor in digital TV tuner application, a new technique of multiple gated transistors in self-biasing basis is presented. The proposed design decreases the bill-of-material (BOM) and offers less complexity for the structure. In addition, the proposed transconductor with third-order Chebyshev introduces a low-pass filter with low power consumption and a cut-off frequency of 50–200 MHz. The hybrid tracking low-pass filter is designed to overcome the issue of local oscillator harmonic-mixing for the Advanced Television System Committee terrestrial digital TV tuner integrated circuit. The proposed operational transconductor amplifier (OTA) is designed and implemented in 90 nm complementary metal-oxide semiconductor technology. The simulation result with a two-tone test at 100 MHz centre frequency proves that the proposed OTA has 5 dBm input-referred third-order intercept point (IIP3) compared with a single-gate OTA in the third-order Chebyshev filter. The proposed OTA achieves the maximum noise figure (NF) of 13 dB and maximum IIP3 of approximately 21.7 dBm at 100 MHz, whereas consuming 18 mA with 1.2 V supply voltage it shows great improvement compared to recent research works.

A 50- to 300-MHz CMOS <inline-formula> <tex-math notation="LaTeX">$Gm\mbox{-}C$</tex-math></inline-formula> Tracking Filter Based on Parallel Operation of Saturation and Triode Transconductors for Digital TV Tuner ICs

In this brief, a 50- to 300-MHz CMOS Gm-C tracking low-pass filter has been presented to resolve a LO harmonic-mixing problem for Advanced Television Systems Committee terrestrial and cable digital TV tuner integrated circuits. A Gm-C filter based on parallel operation of a transconductor biased in the saturation region with source degeneration and a transconductor biased in the triode region is chosen to achieve high linearity performance at the very high frequency/ultrahigh frequency bands. The cutoff frequency of the proposed filter is tunable from 50 to 300 MHz. The filter is implemented in a 0.18-μm CMOS technology and achieves a minimum input-referred noise density of 3 nV/√Hz and maximum in-band output-referred third-order intercept point of 20.7 dBm. It operates at a nominal supply voltage of 1.8 V with bias currents of 114 mA. The active die area is 1.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Highly linear low-pass Gm − C filter with self-biasing transconductor for digital TV tuner

Highly linear low-pass Gm − C filter with self-biasing transconductor for digital TV tuner

Wideband Planar Monopole Antennas for the Brazilian Digital TV System

This paper presents the design, construction and measurements (both at device and system level) of two different planar monopole antennas for the use in the receiving site of a Brazilian Digital TV System, operating in Ultra-High Frequency Range. The design goals were towards low cost, robustness and small volume antennas, for indoor applications and with good performance in terms of return loss within the frequency band. The antennas were designed and optimized using a full wave electromagnetic solver and had their performance compared to an ordinary wire monopole. The scattering parameters were simulated and measured as well as their performance when connected to a digital TV tuner and to a spectrum analyzer, in a dense urban indoor environment was evaluated, as well.

A 40 M–1000 MHz 77.2‐dB spurious free dynamic range CMOS RF variable gain amplifier for digital TV tuner ICs

SummaryIn this paper, a 40 M–1000 MHz 77.2‐dB spurious free dynamic range (SFDR) CMOS RF variable gain amplifier (VGA) has been presented for digital TV tuner applications. The proposed RFVGA adopts a wideband operational‐amplifier‐based VGA and a wideband buffer with differential multiple gated transistor linearization method for wideband operation and high linearity. The SFDR of the proposed RFVGA is also analyzed in detail. Fabricated in a 0.13‐µm CMOS process, the RFVGA provides 31‐dB gain range with 1‐dB gain step, a minimum noise figure of 7.5 dB at a maximum gain of 27 dB, and maximum in‐band output‐referred third‐order intercept point of 27.7 dBm, while drawing an average current of 27.8 mA with a supply voltage of 3.3 V. The chip core area is 0.54 mm × 0.4 mm. Copyright © 2014 John Wiley &amp; Sons, Ltd.

A wideband CMOS inductorless low noise amplifier employing noise cancellation for digital TV tuner applications

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2–15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point (IP1dB) is − 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5 × 0.35 mm2.

지상파 및 케이블 디지털 TV 튜너를 위한 RF 프런트 엔드

This paper presents an integrated low noise and highly linear wideband RF front-end for a digital terrestrial and cable TV tuner, which are used as a part of double-conversion TV tuner. The low noise amplifier (LNA) has a low noise figure and high linearity by adopting a noise canceling technique based on current amplification. The up-conversion mixer and SAW buffer have high linearity by employing a third order intermodulation cancellation technique. The proposed RF front-end is designed in a CMOS and draws 60 mA from a 1.8 V supply voltage. The RF front-end shows a voltage gain of 30 dB, an average single side-band noise figure of 4.2 dB, an IIP2 of 40 dBm, and an IIP3 of -4.5 dBm for the entire band from 48 MHz to 862Hz.

A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process

A low power fully integrated digital TV tuner chip for China Mobile Multimedia Broadcasting (CMMB) application is presented. Based on direction conversion architecture, analog 8th-order filter/gain stages utilizing high power efficient operation-amplifiers and a ΣΔ fractional-N phase locked loop (PLL) with one voltage controlled oscillator (VCO) covering 4.8–7.2 GHz is proposed for low power and small chip area. The tuner is implemented in 65 nm CMOS process with low noise amplifier (LNA) matching network and phase locked loop (PLL) filter integrated on chip, occupying a chip area of 4.83 mm2. The measured noise figure (NF) is less than 3.2 dB over CMMB UHF band (470–798 MHz). A total power consumption of 65 mW (54 mA from 1.2 V supply) is achieved.

Proposal of Multiple Detection Method in Human Detection System using Terrestrial Digital TV Waves

This paper newly proposes Multiple Detection (MD) method in the human detection system using terrestrial digital TV broadcasting waves. In the conventional human detection system using analog TV waves, human motion in a room can be detected by monitoring Received Signal Strength Indicator (RSSI) of the TV waves. The human detection system using TV waves works in the environments where there are no disturbances such as moving car and passing human outside the room. However, the digitalization of the terrestrial TV system deteriorates the detection performance of this system even in such environments. The radio propagation properties of the digital TV system are different from those of the analog one since the digital system is operated in the Single Frequency Network (SFN). In the SFN environment, there are some rooms under the condition that the received TV waves come from several broadcasting stations with same frequency. In such case, our measurement results indicate that the RSSI hardly fluctuates even under condition of human presence and the detection method only using RSSI has a possibility of overlooking the human motion. In the proposed MD method, not only RSSI but also Carrier to Noise Ratio (CNR) and Bit Error Rate (BER) are utilized for human detection. Today most digital TV tuners are capable of monitoring the quality of received signal, such as CNR and BER in addition to RSSI. In this paper, based on the practical measurements by using the digital TV tuners, we evaluate the fluctuation performances of RSSI, CNR and BER affected by human motion in a wooden detached house, and clarify that the MD method can effectively detect human motion even in the SFN environment.

Noise Canceling Balun-LNA with Enhanced IIP2 and IIP3 for Digital TV Applications

An inductorless low noise amplifier (LNA) with active balun for digital TV (DTV) applications is presented. The LNA exploits a noise cancellation technique which allows for simultaneous wide-band impedance matching and low noise design. The matching and amplifier stages in the LNA topology perform single-ended to differential signal conversion with balanced output. The second and third-order nonlinearity of the individual amplifiers as well as the distortion caused by the interaction between the stages are suppressed to achieve high IIP2 and IIP3. A method for intrinsic cancellation of the second-order interaction is employed to reduce the dependence of the IIP3 on the frequency spacing between the interfering signals in the two-tone test of DTV tuners. Fabricated in a 0.18µm CMOS technology, the LNA core size is 0.21mm2. Measurements show that the LNA IIP3 and IIP2 are +12dBm and +21dBm, respectively. The IIP3 variation is less than 5dB in the 10MHz to 200MHz frequency spacing range. A voltage gain of 14.5dB and a noise figure below 4dB are achieved in a frequency range from 100MHz to 1GHz. The LNA consumes 11mA from a 1.8V supply voltage.

A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology

In this paper, a 48-200 MHz CMOS hybrid tracking low-pass filter with low power and high dynamic range is presented to solve a local oscillator harmonic-mixing problem for Advanced Television Systems Committee terrestrial digital TV tuner integrated circuits. For low power consumption, the first-order passive RC filter and the second-order transconductor-C filter are combined to implement the third-order Chebyshev tracking low-pass filter. A transconductor linearization technique based on a method of multiple gated transistors is adopted to achieve high dynamic range. Fabricated in a 0.18 μm CMOS process, it achieves a maximum in-band input-referred noise density of 5.1 nV/√Hz and maximum in-band output-referred third-order intercept point of 17.3 dBm, while dissipating 23.4 mW with 1.8 V. The total chip area is 0.6 mm × 0.4 mm.

CMOS on-chip active RF tracking filter for digital TV tuner ICs

A full frequency band active RF tracking filter design for a digital TV tuner is implemented for the first time. By combined control of the Gm and C values in the biquad of the Gm - C filter, the proposed tracking bandpass filter satisfies full frequency band tuning while maintaining narrow bandwidth. The Gm cell of the tracking filter is based on a dynamic source degenerated differential pair with optimised transistor size ratio, which provides good linearity and high-frequency operation. The fabricated tracking filter based on a 0.13 μm CMOS process shows 48 780 MHz tracking range with 15 60 MHz bandwidth, more than 50 dB of third-order harmonic rejection, 14 dB unwanted signal rejection at N + 6 channel offset, and a maximum IIP3 of 3.8 dBm at 4.7 dB gain while drawing 30 mA from a 1.2 V supply.

A CMOS harmonic rejection mixer based on current mirror amplifiers

A harmonic rejection mixer (HRM) with current mirror amplifier for digital TV tuner applications is proposed. In the proposed HRM, gain ratio can be set accurately using the current mirror amplifier to achieve high harmonic rejection ratio without mismatch calibration circuits. Owing to a folded switching stage, a harmonic rejection ratio of the HRM is also immune to a supply voltage variation and the HRM can be designed at a lower supply voltage compared to a conventional HRM. A third and fifth-order harmonic rejection ratio of the proposed HRM are 52.6 and 50.8dB. The harmonic rejection mixer consumes 11.5mA from 1.5V supply voltage.

A Low Power and Low Noise On-Chip Active RF Tracking Filter for Digital TV Tuner ICs

In this paper, a highly linear and low noise CMOS active RF tracking filter for a digital TV tuner is presented. The Gm cell of the Gm-C filter is based on a dynamic source degenerated differential pair with an optimized transistor size ratio, thereby providing good linearity and high-frequency operation. The proposed RF tracking filter architecture includes two complementary parallel paths, which provide harmonic rejection in the low band and unwanted signal rejection in the high band. The fabricated tracking filter based on a 0.13µm CMOS process shows a 48∼860MHz tracking range with 30-32dB 3rd order harmonic rejection, a minimum input referred noise density of 2.4nV/√Hz, and a maximum IIP3 of 0dBm at 3dB gain while drawing 39mA from a 1.2-V supply. The total chip area is 1mm × 0.9mm.

A CMOS Active Feedback Balun-LNA With High IIP2 for Wideband Digital TV Receivers

A wideband active feedback single-to-differential (S-to-D) low-noise amplifier (LNA) for digital TV (DTV) tuners composed of a S-to-D converter, a voltage combiner, and a negative feedback network is proposed to achieve low noise as well as to improve the linearity performances (IIP2 and IIP3) simultaneously. By feeding the single-ended output of the voltage combiner, which is used for combining the differential output of the S-to-D converter, to the input of the LNA through the feedback network, a wideband S-to-D LNA exploiting negative feedback is implemented. The differential mode operation of the voltage combiner reduces the second-order nonlinearity feedback, allowing us to improve both the IIP3 and IIP2 of the LNA at the same time. Two LNA design examples are presented to demonstrate usefulness of the proposed approach. The LNA I, by adopting a common source (CS) amplifier with a common gate, common source (CGCS) balun load as the S-to-D converter, is able to achieve a high gain and a low noise figure (NF) by increasing the loop gain. The LNA II using the differential amplifier with the ac-grounded second input terminal is designed for robust IIP2 to PVT variations.

A CMOS Wideband RF Front-End With Mismatch Calibrated Harmonic Rejection Mixer for Terrestrial Digital TV Tuner Applications

A wideband direct-conversion RF front-end for Advanced Television Systems Committee terrestrial digital TV (DTV) tuner applications is realized in a 0.18-μm CMOS technology. In order to effectively solve the critical local oscillator (LO) harmonic mixing problem in an ultra-wideband frequency environment of 48-860 MHz, the combination of a mismatch calibrated harmonic rejection mixer (HRM) and a simple preceding integrated third-order passive RF tracking filter with an external inductor is utilized to obtain 60-80 dB of harmonic rejection for all odd-order harmonic mixing within the DTV spectrum. In addition, an efficient novel calibration algorithm for the HRM is proposed in order to simplify the compensation process. The RF front-end also includes a broadband noise-canceling low-noise amplifier, an attenuator to cover the wide dynamic range, an LO multiphase generator, and peripheral circuits such as an I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> C serial interface for digital control. The implemented CMOS RF front-end achieves a total gain of 40 dB, output third-order intercept point of 30 dBm, and noise figure of 5.5 dB while consuming a low power of 140 mW from a 1.8-V supply voltage.

A CMOS Sub-GHz Wideband Low-Noise Amplifier for Digital TV Tuner Applications

A high performance highly integrated sub-GHz wideband differential low-noise amplifier (LNA) for terrestrial and cable digital TV tuner applications is realized in 0.18 μm CMOS technology. A noise-canceling topology using a feed-forward current reuse common-source stage is presented to obtain low noise characteristics and high gain while achieving good wideband input matching within 48―860 MHz. In addition, linearization methods are appropriately utilized to improve the linearity. The implemented LNA achieves a power gain of 20.9 dB, a minimum noise figure of 2.8 dB, and an OIP3 of 24.2 dBm. The chip consumes 32 mA of current at 1.8 V power supply and the core die size is 0.21 mm 2 .

Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 n ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400---3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to the target frequency by setting the coarse-tuning code prior to the start of phase lock. A programmable charge pump is used to reduce variations in PLL characteristics over the frequency range. The synthesizer has been fabricated in a 0.18 μm CMOS technology and the die area is 1.7 � 1.6 mm2. It consumes 27 mA from a 1.8 V power supply. Measurement results show operation of the proposed divide-by-3 circuit over the entire VCO frequency range. The synthesizer quadrature output phase noise for UHF and VHF bands is <�131dBc/Hz at 1.45 MHz offset.