Digital-to-analog Converter Core Research Articles

A 1.2 GSps, 8 bit RF DAC for multi-Nyquist applications in GaAs technology

High-speed digital-to-analog converter (DAC) is key component in instrument and automatic test equipment, radar and ultra-wideband (UWB) systems. In this paper, a two-channel 1.2 GSps, 8 bit RF DAC for Multi-Nyquist applications in 1 µm GaAs Technology is presented. Combining mode select circuit with synchronous latch simplifies design of the current source and layout of DAC core circuit. Measurement results demonstrate that the Differential Nonlinearity (DNL) is within ±0.15 LSB, and the Integral Nonlinearity (INL) is within ±0.4 LSB. For the normal mode, the Spurious Free Dynamic range (SFDR) is larger than 40 dB; for the mixing mode, output bandwidth is up to 1.8 GHz, and the SFDR is larger than 30 dB. Under a supply voltage of 5 Volts, the output swing is 1.1 Vpp, and the total power consumption is 1.7 Walts for both channels working.

A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in <inline-formula> <tex-math notation="LaTeX">$0.18~\mu $ </tex-math></inline-formula>m CMOS

In this brief, a 14-bit 500 MS/s current-steering digital-to-analog converter (DAC) is proposed, which applies the novel grouped random rotation thermometer code (GRTC) and the differential-quad switching (DQS) and has good dynamic performance without calibrations. The GRTC suppresses the harmonics caused by element mismatches, while the DQS reduces the input-code transition-dependent distortion to achieve a high spurious-free dynamic range (SFDR). A unit current cell with an intrinsic precision of 12 bits rather than 14 bits is used to reduce the active area, and the simple diagonal structure with a common-centroid layout is adopted to reduce the gradient error. The measured SFDR of the proposed DAC is more than 80 dBc below 35 MHz and better than 68 dBc over the entire Nyquist bandwidth. The power consumption of the DAC core is only 67.7 mW at 500 MS/s. The proposed DAC has been implemented in the Semiconductor Manufacturing International Corporation (SMIC) 0.18- $\mu $ m CMOS process and occupies an active area of only 0.55 $\mathrm{mm}^{\mathrm {\mathbf {2}}}$ .

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with the IC process variability, a unit element approach is generally employed. The three most significant bit (MSBs) are implemented as seven unary D/A cells and the three least significant bits (LSBs) as three binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5 kb is placed on-chip, which is externally loaded in a serial way but internally read in an 8× time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output nonlinearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC Spurious Free Dyanmic Range >40 dB bandwidth is 0.8 GHz, while the IM3 <;-40 dB bandwidth exceeds 1.3 GHz. The DAC consumes 53 mW of power and the design-for-test scheme -80 mW.

A 10 Gsps 8 bit digital-to-analog converter with a built-in self-test circuit

We present a 10 Gsps 8 bit digital-to-analog converter (DAC) with a novel built-in self-test (BIST) circuit, which makes it possible to evaluate the DAC's performance without a complicated test setup. Design considerations and test results are included. According to the test results, the DAC core and the BIST circuit are able to work under 10 GHz. The chip is fabricated in 0.18 μm SiGe HBTs with ft of 100 GHz. The DAC core occupies a die size of 260 × 250 μm2.

InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With &gt; 70-dB SFDR

A prototype 13-b 1.33-Gsps digital-to-analog converter (DAC) implemented in a unique heterogeneous integration process (combining 0.45-μm InP HBT with 0.18-μm CMOS) is presented. Measured performance of greater than 70 dB SFDR is achieved across a 500-MHz bandwidth centered at 1 GHz (second Nyquist band). Heterogeneous integration enables each circuit element to be implemented in the transistor technology best suited to the circuit function. Low dc power is achieved by implementing the digital front-end in a standard silicon CMOS technology, while InP HBT technology is used to implement the high-speed/high-precision current-steering DAC core. The core DAC employs a segmented architecture with three unary most significant bits and an R-2R ladder for the ten least significant bits. No calibration circuitry is required to achieve better than 11 b of dc linearity. Dynamic performance is enhanced by employing an ultra-high-linearity return-to-zero (RZ) analog output deglitcher switch. Measured performance data for three different circuit design variations of the output switch (incorporating a varying mix of CMOS and InP HBT devices) is presented.

A 10-bit CMOS Capacitive and Resistive D/A Converter Integrated with Self-adjusted Reference Circuit

A 10-bit, digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.5 ¼ complementary metal oxide semiconductor (CMOS) process. The DAC is optimized for system-on-chip (SOC) readout circuits. A capacitive and resistive DAC is adopted for the DAC core to obtain area reduced and good monotony. A self-adjusted reference circuit is proposed in order to provide differential reference voltages for getting better accuracy. A unique common centroid layout is used in the capacitor network to reduce the effect of thermal or process linear gradients. The measured results of our work with integral non-linearity (INL) and differential non-linearity (DNL) are less than 0.54 LSB and 0.43 LSB, respectively. The power consumption is about 16 mW.

A Pseudodifferential Class AB DAC for Low-Power Wireless Transmitter

A low spurious 12-bit 122.88-MS/s digital-to-analog converter (DAC) enabling a low-power wireless transmit (Tx) chain is proposed and demonstrated. Pseudodifferential class AB DACs are introduced, and the benefits of using them in wireless Tx paths are discussed. The major power savings are achieved in multistage baseband Tx filters and upconversion mixers by using code-dependent linearly scaled dc that is generated from class AB transmit DACs. A two-channel I/Q DAC core consumes 6 mA with a 1.3/2.2-V dual supply. The 0.18-mm2 I/Q DAC core fabricated in a 65-nm digital CMOS process, along with a highly integrated digital baseband processor and radio frequency transceiver, achieves a 73-dB spurious free dynamic range, 61-dB signal-to-noise-plus-distortion ratio, and -70-dB total harmonic distortion for a 990-kHz sinusoid at a 122.88-MS/s sample rate.

A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter

A low-spurious low-power 12-bit 160-MS/s digital to analog converter (DAC) for baseband wireless transmitter is proposed and demonstrated. Degenerated current switches are introduced and benefits of using them are discussed. Mismatch behavior under packaging-induced die stress is also presented. The mobility shift caused by package stress inherited from a thin-die is a dominant source of I/Q mismatch. A 2-channel I/Q DAC core consumes 4 mA with a 1.3/2.6 V dual supply. The 0.13 mm2 I/Q DAC core fabricated in 90-nm digital CMOS process with a highly-integrated digital processor achieves 74 dB SFDR, 55 dB SNDR, and -73 dB THD for a 975 kHz sinusoid at 153.6 MS/s sample rate.

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.