Digital Subscriber Line Applications Research Articles

Timing error estimation for baseband multicarrier modulation

AbstractIn this paper, the topic of timing error estimation for baseband discrete multitone modulation is addressed in the context of high‐speed digital subscriber line applications. To the authors' best knowledge, this problem is sparsely and not in depth treated in the literature. In this study the modified Cramer–Rao lower bound is derived, two conventional estimators are considered and a new one is proposed. Behavior of these estimators is evaluated in terms of bias, variance and computational complexity in a wide variety of scenarios, concluding that the proposed estimator appears to be superior in all instances. Copyright © 2008 John Wiley & Sons, Ltd.

A 2.5-V 14-bit, 180-mW Cascaded $\Sigma\Delta$ ADC for ADSL2+ Application

This paper presents a sigma-delta (SigmaDelta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 SigmaDelta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 d 15 and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-mum CMOS technology, in a 2.8 mm2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.

Interpolated decision feedback equalization for long intersymbol interference channels

The decision feedback equalizer (DFE) is widely used in communication systems combating intersymbol interference effect. In wireline communications, the channel response is usually long and the computational complexity of the DFE is often high. This is particularly true when the precoding is applied in which the feedback signal value becomes continuous rather than discrete. In this paper, an interpolated DFE (IDFE) structure is proposed to solve the problem. The proposed IDFE consists of a finite-impulse-response (FIR) feedforward filter and an interpolated FIR feedback filter. Thanks to the interpolation operation, the computational complexity of the DFE can be greatly reduced. The least-mean-squared (LMS) algorithm is applied to train the tap weights yielding an adaptive IDFE. Closed-form expressions for optimal filter coefficients, mean squared errors, and signal-to-noise ratios are derived. The convergence behavior of the adaptive IDFE is also analyzed. Simulation results show that while the computational complexity is significantly reduced, the performance of the proposed IDFE is similar to the conventional DFE. The computational saving can be as high as 76% for a high-speed digital subscriber line application.

Nonlinearity correction for multibit /spl Delta//spl Sigma/ DACs

This paper presents a digital correction technique for wide-band multibit error-feedback (EF) digital-to-analog converters (DACs). The integral nonlinearity (INL) error of the multibit DAC is estimated (on line or off line) by a calibration analog-to-digital converter (CADC) and stored in a random-access memory table. The INL values are then used to compensate for the multibit DAC's distortion by a simple digital addition. The accuracy requirements for the error estimates are derived. These requirements can be significantly relaxed when the correction is combined with data-weighted averaging (DWA). Simulation and discrete-component measurement results are presented for a fourth-order 5-bit EF DAC. The results show a 14-bit DAC operating at an oversampling ratio of 8, which is suitable for digital subscriber line applications. The correction uses simple digital circuitry and a 3-bit CADC enhanced by DWA.

Highly Linear 2.5-V CMOS>tex<$Sigma Delta $>/tex<Modulator for>tex<$hboxADSL+$>/tex<

We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator.

Use of the reference noise method bounds the performance loss due to upstream power backoff

This paper presents mathematical proofs that the performance loss due to using the reference noise method of upstream power backoff is bounded. First, it is shown that when two lines of arbitrary lengths are considered, application of the reference noise method results in an upstream signal-to-noise ratio (SNR) degradation of less than 3 dB relative to when the two loops are the same length and the remote transceivers transmit at the maximum allowed power spectral density. Next, an extension to the reference noise method is introduced, and it is shown that the 3-dB bound holds for an arbitrary number of lines. Finally, the reference noise method is shown to minimize the maximum SNR loss relative to when all lines are the same length and all remote transceivers transmit at the maximum allowed power spectral density. The result is significant for very high-speed digital subscriber line applications because it allows service providers to determine a priori the worst case impact of upstream power backoff on upstream bit rates without consideration of the loop plant topology.

Maximizing the channel capacity of multicarrier transmission by suitable adaptation of the time-domain equalizer

An adaptation algorithm for determining the time-domain equalizer coefficients is described that maximizes the total channel capacity for all carriers of a multitone (discrete multitone) transmission. It takes into account the crosstalk noise environment and the interblock interference as a common disturbance. Furthermore, the leakage effect of the discrete Fourier transform (fast Fourier transform) is considered, too. Including this into the algorithm for the equalizer coefficients leads to a notable improvement in the signal-to-noise ratio, especially at lower frequencies for a typical asymmetrical digital subscriber line application.

A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications

The design of a high-resolution, high-speed, delta-sigma analog to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-/spl mu/m CMOS technology, in a 5-mm/sup 2/ die area, and consumes 200 mW from a 3.3-V power supply.