Digital Signal Processor Programming Research Articles

DSP Implementation of a Neural Network Vector Controller for IPM Motor Drives

This paper develops a neural network (NN) vector controller for an interior mounted permanent magnet (IPM) motor by using a Texas Instrument TMS320F28335 digital signal processor (DSP). The NN controller is developed based on the complete state-space equation of an IPM motor and it is trained to achieve optimal control according to approximate dynamic programming (ADP). A DSP-based NN control system is built for an IPM motor drives system, and a high efficient DSP program is developed to implement the NN control algorithm while considering the limited memory and computing capability of the TMS320F28335 DSP. The DSP-based NN controller is able to manage IPM motor control in linear, over, and six-step modulation regions to improve the efficiency of IPM drives and to allow for the full utilization of DC bus voltage with space-vector pulse-width modulation (SVPWM). The experiment results show that the proposed NN controller is able to operate with a sampling period of 0.1ms, even with limited DSP resources of up to 150 MHz cycle time, which is applicable in practical motor industrial implementations. The NN controller has demonstrated a better current and speed tracking performance than the conventional standard vector controller for IPM operation in both the linear and over-modulation regions.

An Energy Metering and Measurement SoC With a Novel Low-Power DSP Architecture

This paper presents an energy metering and measurement system-on-a-chip (SoC) with a novel low-power digital signal processor (DSP) architecture. The Cotex-M0-based SoC can measure electricity signals and meter active and reactive energy. It can also monitor the grid by directly accessing and analyzing the waveforms. The measurement and metering algorithms are implemented in a novel DSP architecture with a dedicated reduced instruction set. The filter coefficients and its operating frequency in the default program of DSP can be reprogrammed independently. It can be applied in different applications where demands for metering bandwidth and response time are different. The DSP program can also be reprogrammed by the software if the default program is not desired. The SoC is implemented in a 0.11- ${\mu }\text{m}$ CMOS process. It achieves active and reactive energy metering accuracy of 0.1% with a dynamic range of 5000:1. The analog power supply is 3.3 V and the digital power supply is 1.8 V. The total power consumption of the SoC is ca 17.63 mW with the DSP consuming ca 1.0 mW. Compared with other commercial metering and measurement SoCs, the presented SoC achieves higher metering accuracy and lower power consumption. It is currently in production.

Extending Halide to Improve Software Development for Imaging DSPs

Specialized Digital Signal Processors (DSPs), which can be found in a wide range of modern devices, play an important role in power-efficient, high-performance image processing. Applications including camera sensor post-processing and computer vision benefit from being (partially) mapped onto such DSPs. However, due to their specialized instruction sets and dependence on low-level code optimization, developing applications for DSPs is more time-consuming and error-prone than for general-purpose processors. Halide is a domain-specific language (DSL) that enables low-effort development of portable, high-performance imaging pipelines—a combination of qualities that is hard, if not impossible, to find among DSP programming models. We propose a set of extensions and modifications to Halide to generate code for DSP C compilers, focusing specifically on diverse SIMD target instruction sets and heterogeneous scratchpad memory hierarchies. We implement said techniques for a commercial DSP found in an Intel Image Processing Unit (IPU), demonstrating that this solution can be used to achieve performance within 20% of highly tuned, manually written C code, while leading to a reduction in code complexity. By comparing performance of Halide algorithms using our solution to results on CPU and GPU targets, we confirm the value of using DSP targets with Halide.

Dynamic Simulation Test Research on Power Fluctuation Compensation Using Hybrid SMES of YBCO and BSCCO Tapes

A kJ class high temperature superconducting magnetic energy storage system (HTS-SMES) composed of YBCO and BSCCO coils with a cryogenic system using sub-cooled LN2 is optimal designed. This SMES is applied for the dynamic power fluctuation compensation considering the quench protection in power system. A dual processor combined with the digital signal processor (DSP) and the micro-programmed control unit (MCU) is proposed to construct a LCL filtered voltage source converter system for the SMES. Based on the SVPWM pulse modulation, the power fluctuation compensation strategy of the SMES and its DSP programs are proposed. Finally, a dynamic simulation test system with this SMES for compensation of power fluctuation is build up and the electric power experimental results show that the SMES can output the required compensation power correctly and restrain the power fluctuation in milliseconds.

Digital analysis and sorting of fluorescence lifetime by flow cytometry

Frequency-domain flow cytometry techniques are combined with modifications to the digital signal-processing capabilities of the open reconfigurable cytometric acquisition system (ORCAS) to analyze fluorescence decay lifetimes and control sorting. Real-time fluorescence lifetime analysis is accomplished by rapidly digitizing correlated, radiofrequency (RF)-modulated detector signals, implementing Fourier analysis programming with ORCAS' digital signal processor (DSP) and converting the processed data into standard cytometric list mode data. To systematically test the capabilities of the ORCAS 50 MS/sec analog-to-digital converter (ADC) and our DSP programming, an error analysis was performed using simulated light scatter and fluorescence waveforms (0.5-25 ns simulated lifetime), pulse widths ranging from 2 to 15 micros, and modulation frequencies from 2.5 to 16.667 MHz. The standard deviations of digitally acquired lifetime values ranged from 0.112 to >2 ns, corresponding to errors in actual phase shifts from 0.0142 degrees to 1.6 degrees. The lowest coefficients of variation (<1%) were found for 10-MHz modulated waveforms having pulse widths of 6 micros and simulated lifetimes of 4 ns. Direct comparison of the digital analysis system to a previous analog phase-sensitive flow cytometer demonstrated similar precision and accuracy on measurements of a range of fluorescent microspheres, unstained cells, and cells stained with three common fluorophores. Sorting based on fluorescence lifetime was accomplished by adding analog outputs to ORCAS and interfacing with a commercial cell sorter with a RF-modulated solid-state laser. Two populations of fluorescent microspheres with overlapping fluorescence intensities but different lifetimes (2 and 7 ns) were separated to approximately 98% purity. Overall, the digital signal acquisition and processing methods we introduce present a simple yet robust approach to phase-sensitive measurements in flow cytometry. The ability to simply and inexpensively implement this system on a commercial flow sorter will allow both better dissemination of this technology and better exploitation of the traditionally underutilized parameter of fluorescence lifetime.

Adaptive control of force microscope cantilever dynamics

Magnetic resonance force microscopy (MRFM) and other emerging scanning probe microscopies entail the detection of attonewton-scale forces. Requisite force sensitivities are achieved through the use of soft force microscope cantilevers as high resonant-Q micromechanical oscillators. In practice, the dynamics of these oscillators are greatly improved by the application of force feedback control computed in real time by a digital signal processor (DSP). Improvements include increased sensitive bandwidth, reduced oscillator ring up/down time, and reduced cantilever thermal vibration amplitude. However, when the cantilever tip and the sample are in close proximity, electrostatic and Casimir tip-sample force gradients can significantly alter the cantilever resonance frequency, foiling fixed-gain narrow-band control schemes. We report an improved, adaptive control algorithm that uses a Hilbert transform technique to continuously measure the vibration frequency of the thermally-excited cantilever and seamlessly adjust the DSP program coefficients. The closed-loop vibration amplitude is typically 0.05 nm. This adaptive algorithm enables narrow-band formally-optimal control over a wide range of resonance frequencies, and preserves the thermally-limited signal to noise ratio (SNR).

A real-time formant tracker based on the inverse filter control method

Formant frequencies are very important speech features in the area of speech perception and practical application. Although some formant estimation methods have been proposed previously, those have been inferior in real-time operation. Previously, we have proposed a new type of formant estimation based on IFC (Inverse Filter Control) method and applied into speech analysis and application systems in our study. Since the IFC method is based on speech waveform processing, the realization of a real-time system has been expected. On the other hand, recently the cheap electric boards which mounted a very high-speed DSP (Digital Signal Processor) have been marketed. We have applied such a DSP board into developing a real-time formant tracker based on the IFC method. By correcting the original C-language program for DSP operation, we have confirmed the real-time operation, which have estimated four formant frequencies from F1 to F4. Moreover, those estimates were almost the same as those by the original PC simulation. In this paper, we describe system modification for DSP realization and discuss effects of software modifications from C-language into DSP program.

SoC with an integrated DSP and a 2.4-GHz RF transmitter

We present a system-on-chip (SoC) that integrates a TMS320C54x digital signal processor (DSP), which is commonly used in cellular phones, with a multigigahertz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital phase-locked loop (ADPLL), which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicrometer CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. As part of the digital flow, the digitally controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/Os. All digital blocks, including the 2.4-GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130-nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The RF transmitter area occupies only 0.54 mm/sup 2/, and the current consumption (including the companion DSP) is 49 mA at 1.5-V supply and 4 mW of RF output. This proves attractiveness and competitiveness of the "digital RF" approach, whose goal is to replace RF functions with high-speed digital logic gates.

Minimization of Data Address Computation Overhead in DSP Programs

Modern digital signal processors (DSPs) provide dedicated address generation units (AGUs) which support data memory access by indirect addressing with automatic address modification in parallel to other machine operations. There is no address computation overhead if the next address is within the auto-modify range. Typically, optimization of data memory layout and address register assignment allows to reduce both execution time and code size of DSP programs. In this paper, we present an optimization technique for integrated data memory layout generation and address register assignment. We use a generic AGU model which captures important addressing capabilities of DSPs such as linear addressing, modulo addressing, auto-modifying, and indexing within a given auto-modify range. Experimental results demonstrate that the proposed technique significantly outperforms existing optimization strategies.

Power analysis and minimization techniques for embedded DSP software

Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged.

A direct current superconducting quantum interference device gradiometer with a digital signal processor controlled flux-locked loop and comparison with a conventional analog feedback scheme

A double-washer dc superconducting quantum interference device (SQUID) gradiometer with a flux-locked loop (FLL) based on a digital signal processor (DSP) has been developed for biomagnetic applications. All of the analog electronics in the conventional FLL are replaced and implemented by the DSP except for the low-noise field-effect transistor preamplifier at the front end of the signal recovery components. The DSP performs the signal demodulation by synchronously sampling the recovered signals and applying the appropriate full wave rectification. The signals are then integrated, filtered, and applied to the output. At 4.2 K, the white flux noise of the gradiometer measured in a DSP FLL mode is about 4μΦ0/√Hz and the noise at 1 Hz is 13 μΦ0/√Hz. The corresponding noise levels in the gradiometer operated by the conventional FLL are 1.8 and 3μΦ0/√Hz. The poorer system performance in the DSP FLL compared to the analog FLL is mainly caused by the ambient field noise and interference signals picked up through the connecting cables. Additional noise is also added to the overall noise floor by the instruments employed in the DSP system in the present prototype setup. Further improvement in the noise characteristics and the dynamic behavior of the DSP SQUID gradiometer is expected when a better configuration of DSP with the associated I/O devices is implemented. Additional improvements of the DSP programs are expected by incorporating higher-order integration, adaptive control, and noise reduction schemes.

Digital Signal Processor: Software Simulator

One of the development aids for the digital signal processor (DSP) is a software simulator, dspsim, which runs interactively under the UNIX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∗</sup> operating system. It is a program debugging tool which can be used without access to the DSP hardware environment. It allows the user to monitor run-time characteristics of DSP programs which cannot be observed using the device itself. It is very flexible in providing capabilities for single or multiple program stepping, setting and modifying conditional breakpoints, examining register contents and generating data plots on the terminal.

Digital Signal Processor: Private Communications

Where normal safeguards for message privacy are not adequate, some form of encryption is required. Voice messages, encoded using an adaptive differential pulse-code-modulation encoder such as that described in a companion paper, may be encrypted for privacy (protection against casual eavesdropping) through similar digital signal processor programs with little additional computation. Two methods of implementation are described: The use of U-permutations for temporal scrambling of the transmitted bit stream and the use of bit masking by stored random numbers. The relative merits of each system are discussed, illustrating both the flexibility and limitations of the digital signal processor for such applications.