Digital Signal Processing Architectures Research Articles

Multidimensional QPSK symbol modulation scheme based on random sequence extraction for D-band photonics-aided wireless communication

We propose a multidimensional (MD) quadrature phase shift keying (QPSK) symbol modulation and demodulation scheme based on random sequence extraction, which overcomes the limitations of traditional QPSK signals in performing probabilistic shaping. Unlike probabilistic shaping (PS) and geometric shaping (GS), our approach does not require modifications to the existing digital signal processing (DSP) architecture; it only necessitates the addition of sequence modulation and demodulation modules. Additionally, the source entropy (SE) can be flexibly adjusted. An experimental verification was conducted in a 50 m, 150 GHz photonics-aided wireless communication system. The results show that, under the same net data rate, the random sequence extraction QPSK scheme can achieve a maximum optical power gain of 0.7 dB. These findings indicate that the random sequence extraction QPSK (SE-QPSK) scheme can effectively enhance system performance, providing a promising outlook for future wireless communication.

Design of Energy Efficient Arithmetic VLSI Circuits

Advanced electronics have become an integral part of human lives, from Smartphones in our pockets to the modern vehicles on the road and to the satellites that orbit the earth. Power consumption has become a major constraint in these applications, often employing data- intensive digital signal processing systems and architectures. While enormous transistor density at the nanoscale has been increased in the Very Large-Scale Integration (VLSI) multicore era comparable to Moore's law, improving the performance of computing systems has become extremely difficult. Sustaining technological advancements for such energy-constrained devices has paved the way for new areas in research. “Approximate Computing (AC)” has become one of the most promising paradigms, a field that has gainedsignificant attention in the quest for energy efficiency in recent years. AC algorithms are numerically approximate rather than accurate. Inherent error resilience is the primary source of motivation behind AC. Recent research demonstrates that error resilience is pervasive in cyber search, deep learning, multimedia, recognition and data mining. Arithmetic units are the fundamental building blocks in most of the data dominated applications at the micro- architectural level of abstraction. AC is optimal for power and area efficient arithmetic circuits.

FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick’s signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively.

Wideband Array Signal Processing with Real-Time Adaptive Interference Mitigation.

Wideband beamforming and interference cancellation for phased array antennas requires advances in signal processing algorithms, software, and specialized hardware platforms. A high-throughput array receiver has been developed that enables communication in radio frequency interference-rich environments with field programmable gate array (FPGA)-based frequency channelization and packetization. In this study, a real-time interference mitigation algorithm was implemented on graphics processing units (GPUs) contained in the data pipeline. The key contribution is a hardware and software pipeline for subchannelized wideband array signal processing with 150 MHz instantaneous bandwidth and interference cancellation with a heterogeneous, distributed, and scaleable digital signal processing (DSP) architecture that achieves 30 dB interferer cancellation null depth in real time with a moving interference source.

Adaptive parallel decision deep neural network for high-speed equalization.

The equalization plays a pivotal role in modern high-speed optical wire-line transmission. Taking advantage of the digital signal processing architecture, the deep neural network (DNN) is introduced to realize the feedback-free signaling, which has no processing speed ceiling due to the timing constraint on the feedback path. To save the hardware resource of a DNN equalizer, a parallel decision DNN is proposed in this paper. By replacing the soft-max decision layer with hard decision layer, multi-symbol can be processed within one neural network. The neuron increment during parallelization is only linear with the layer count, rather than the neuron count in the case of duplication. The simulation results show that the optimized new architecture has competitive performance with the traditional 2-tap decision feedback equalizer architecture with 15-tap feed forward equalizer at a 28GBd, or even 56GBd, four-level pulse amplitude modulation signal with 30dB loss. And the training convergency of the proposed equalizer is much faster than its traditional counterpart. An adaptive mechanism of the network parameter based on forward error correction is also studied.

Research on key technologies of multi-core DSP in smart substation redundancy network testing

Aiming at the network characteristics of a smart substation redundant network with complex communication messages, a large amount of interactive data, and high real-time performance, the test model of multiple submachines in a High-Availability Seamless Redundancy (HSR) loop network is analyzed. The requirements of packet types, size, and transmission speed are evaluated, and a hardware solution based on a multi-core Digital Signal Processor (DSP) and Parallel architecture FPGA is designed. The multi-core interaction strategy of DSP software and the multi-port high-speed communication method of FPGA are proposed, and the inter-core communication (IPC) interrupts and shared memory to achieve fast data migration between cores, based on the Serial RapidIO (SRIO) to complete high-speed message transmission. The throughput, delay, packet loss rate, and error frame detection functions are realized, tested, and verified, providing theoretical and practical support for the evaluation of redundant network performance of smart substations.

Real-time transponder architecture for hitless transmission baud rate switching in association with an auto-negotiation protocol

We propose a novel digital signal processing architecture for a coherent receiver that allows instantaneous and hitless variable baud rate transmission for integer sub-division values. This solution allows the receiver to self-adapt a new baud rate without processing modification, re-initialization, or any knowledge of the transmission speed modification. As for implantation concern, this architecture requires negligible extra logic compared to the standard one. Its development and operation developed on a simulation basis are presented; then its dynamic behavior and performance are demonstrated in a real-time experiment attesting a zero-bit loss. We also show how an in-line auto-negotiation protocol between a transmitter and a receiver minimizing the mediation through the control plane can leverage this instantaneous baud rate variation.

Inner Product Computation In-Memory Using Distributed Arithmetic

In-memory computing using emerging technologies such as Resistive Random-Access Memory (ReRAM) has been proposed as a promising substitute for future computing applications to address the ‘von Neumann bottleneck’. Multiplication is the key component for inner product computation in every digital signal processing (DSP) application and the complexity of multipliers increases greatly with bit-width. Distributed arithmetic (DA) using look-up tables and adder-shifter module has been proposed for inner product computation to achieve multiplier-less efficient DSP architectures, particularly when one of the vectors is a constant and known in advance. Due to the memory wall, DA can be made furthermore latency and energy-efficient when implemented ‘in memory’. In this work, for the first time, we propose two design techniques to compute inner product completely in memory using DA. This is accomplished by storing the precomputed look-up table contents in a ReRAM array and implementing adder-shifter module also in the same array. The adder-shifter is implemented in memory using majority gates which are in turn realized as READ operations in the memory array. Two methods of mapping: latency-optimized and area-optimized and their comparison in terms of latency and area are presented. The proposed method-1 achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 60$ </tex-math></inline-formula> % energy savings compared to CMOS and the proposed method-2 achieves 10.59 times higher throughput compared to CMOS.

Development of a dual digital signal processor based cyber-physical system model for a multi-carrier energy system

Multi-energy systems are under exploration for a variety of benefits that can provide multi-energy demands with combined electricity, heat and gas, the most widespread energy demands, to end-users. To satisfy such requirements, this paper integrates a multi-carrier energy system (MCES), including electricity, heat and hydrogen with the cyber-physical system (CPS) model to establish a novel energy CPS. Firstly, the finite state machine (FSM) and the time series method are used to establish a unified CPS architecture of energy nodes. Simultaneously, the embedded architecture of the dual digital signal processor (DSP) system at the energy node level is proposed to implement external control and internal self-control for the energy CPS. Secondly, the CPS modeling method in MCES is conducted by analyzing multi-class energy nodes including energy source nodes, energy conversion nodes, energy storage nodes and energy end-user nodes. Subsequently, the physical system, information system and control system of a reversible solid oxide fuel cell (RSOFC) node and the dynamic operation of MCES are analyzed and simulated by introducing the CPS model, where the controllability and interactivity of the designed energy CPS model are further demonstrated.

Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals

This work presents a soft-filtering digital signal processing architecture based on sigma-delta modulators and stochastic computing. A sigma-delta modulator converts the input high-resolution signal to a single-bit stream enabling filtering structures to be realized using stochastic computing’s negligible-area multipliers. Simulation in the spectral domain demonstrates the filter’s proper operation and its roll-off behavior, as well as the signal-to-noise ratio improvement using the sigma-delta modulator, compared to typical stochastic computing filter realizations. The proposed architecture’s hardware advantages are showcased with synthesis results for two FIR filters using FPGA and synopsys tools, while comparisons with standard stochastic computing-based hardware realizations, as well as with conventional binary ones, demonstrate its efficacy.

Low Complexity DSP for High Speed Optical Access Networking

A novel low-cost and energy-efficient approach for reaching 40 Gb/s signals is proposed for cost-sensitive optical access networks. Our proposed design is constituted of an innovative low-complex high-performance digital signal processing (DSP) architecture for pulse amplitude modulation (PAM-4), reuses existing commercial cost-effective 10-G components and eliminates the need of a power-hungry radio frequency (RF) component in the transmitter. Using a multi-functional 17-tap reconfigurable adaptive Volterra-based nonlinear equalizer with noise suppression, significant improvement in receiver optical power sensitivity is achieved. Results show that over 30 km of single-mode fiber (SMF) a link power budget of 33 dB is feasible at a bit-error-rate (BER) threshold of 10−3.

High Throughput Low Complexity and Low Power ePiBM RS Decoder Using Fractional Folding

This brief proposes a novel generalized Fractional Folding (FF) architecture for digital signal processing integrated circuits. With this new structure, a Fractional Folding based enhanced Parallel Inversionless Berlekamp-Massey (FF-ePIBM) Reed-Solomon Decoder is presented of which the number of processing element (PE) can be reduced to only one, resulting in ultra-low hardware complexity. The FF-ePIBM VLSI architecture can greatly reduce the hardware cost by about 60% compare to the fully expanded parallel ePIBM architecture. With FF-ePIBM architecture, syndrome calculation (SC) block and Chien search & error evaluation (CSEE) block are able to operate at a lower frequency resulting in about 14.8% power saving. A polyphase clock signal is needed in order to achieve fractional folding function according to specific fractional-factor. It is generated from Delay Locked Loop (DLL) at little or no extra cost in different SoCs. To maximize the throughput of decoder, pipelined architecture is adopted to optimize critical path delay. The RS (255, 239) decoder with FF-ePIBM architecture is finally implemented with 40nm CMOS technology. The synthesized results demonstrate that the decoder has a gate count of 12.9k and can operate at 3.1GHz to achieve a highest throughput of 24.8Gb/s and a best TSNT FoM value of 592 to this date.

Simplifying Single-Bin Discrete Fourier Transform Computations [Tips &amp;amp; Tricks

A digital signal processing (DSP) architecture is presented to compute single bins of the discrete Fourier transform (DFT) with low complexity. This architecture consists of a cascade of simple accumulators working at the input sampling rate and a polyphase finite impulse response (FIR) filter with complex coefficients working at a lower rate. The advantage of this structure is that, for several cases, it is possible to have a system with only one accumulator operating in the high-rate section and a low-order FIR filter working in the low-rate section. However, this depends on the index of the frequency bin to be computed (k) and the number of DFT points (N). Advantages and limitations of this approach are presented, and the implementation scheme is elaborated.

A DSP Architecture for Distortion-Free Evoked Compound Action Potential Recovery in Neural Response Telemetry System.

This paper presents a digital signal processing (DSP) architecture for real-time and distortion-free recovery of electrically-evoked compound action potentials (ECAPs) from stimulus artifacts and periodic noises in bidirectional neural response telemetry (NRT) system. In this DSP architecture, a low computation-cost bidirectional-filtered coherent averaging (BFCA) method is proposed for programmable linear-phase filtering of ECAPs, which can be easily combined with the alternating-polarity (AP) stimulation method to reject stimulus artifacts overlapped with ECAP responses. Design techniques including the configurable folded infinite-impulse response (IIR) filter and division-free averaging are also presented for efficient hardware implementation. Implemented in 180-nm CMOS process, the proposed DSP architecture consumes 10.03-mm2 area and 2.35-mW post-layout simulated power. The efficacy of the DSP architecture in recovering ECAPs from recorded neural data contaminated by overlapped stimulus artifacts and periodic noises is validated in in-vivo electrical nerve stimulations. Experiment results show that compared with the previous coherent averaging technique, the proposed DSP architecture improves the signal-to-noise ratio (SNR) of ECAP responses by 11 dB and achieves a 3.1% waveform distortion that is 17.1× lower.

A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth

In the present century, digital signal processing (DSP) approaches are considered to be one of the most powerful technologies which may shape the science and technology in coming decades. From 1970 onwards, a drastic revolution took place in a wider domain of DSP which has made it popular in several studies such as radar and sonar signal processing, digital televisions, wireless communication scenarios and other multimedia setup etc. Digital filters form the backbone of this DSP architecture and in point of fact the field of digital filter design has drawn justified recognition from the researchers throughout the world for the last 50 years. In connection to this, thousands of research articles may be found from the literature which had extensively addressed on the design of such filters. In order to meet the requirement of narrow transition-band, finite impulse response (FIR) filters are commonly assumed to be of higher order and accordingly it significantly enhances computational complexity. In regard to this, construction of hardware efficient digital filters had drawn significant consideration which aims to include minimum hardware elements during its application and consequently consumes less power. This review paper illustrates various techniques for the implementation of hardware efficient narrow transition-band FIR filter and investigates a number of favourable attributes which are capable in sustaining the stringent requirements of communication standards. A good number of relevant articles are taken from the literature so as to make a robust and complete review.

An Efficient Implementation and Analysis of Tail-Biting Convolution Coding Algorithm for OFDM Based System in Terms of Speed, Memory and Peak-to-Average Power Ratio Using DSP

Fourth Generation (4G) mobile communication system uses Orthogonal Frequency Division Multiplexing (OFDM). With this technique, high data rate demands are achieved. Tail biting Convolution Coding (TBCC) avoids the data rate loss, hence it is widely used error control coding algorithm in OFDM and other various wireless communication technologies. But, OFDM has increased Peak to Average Power Ratio (PAPR). High PAPR signal consumes more power and makes system power inefficient. To gain supercomputing performance in terms of Speed, Memory and Power on mobile devices, an efficient implementation of algorithms on Digital Signal Processing (DSP) processor is an essential requirement. This requirement becomes more stringent for Fifth Generation (5G) mobile devices. For this, wide scope of knowledge as well as skills are required to understand the algorithm, DSP architecture, instruction set, optimization and performance measurement. In this article, we have implemented TBCC algorithm using Bit by Bit (BYB) and Look Up Table (LUT) approaches on Freescale StarCore SC140 based DSP platform and proposed an efficient algorithm implementation methodology by comparing the machine cycles and memory requirement. We have used coding rate (R) = 1/2, 1/3, 1/4 and constraint length (K) = 5 and K = 9 for implementation of TBCC. Using our proposed LUT approach, we have achieved average 45.82% Computational Complexity Reduction Ratio (CCRR) in machine cycles compared to BYB approach. Proposed LUT approach increases the TBCC execution speed. Our developed fixed point routines can be used for any K ≤ 9. TBCC is also analyzed for PAPR to get an overall profiling results and three dimensional optimization of TBCC algorithm in terms of Speed, Memory and Power.

A Parallel Timing Synchronization Structure in Real-Time High Transmission Capacity Wireless Communication Systems

In the past few years, parallel digital signal processing (PDSP) architectures have been intensively studied to fulfill the growing demand of channel capacity in coherent optical communication systems. However, to our knowledge, real-time timing synchronization in such architectures is until now not implemented on a Field Programmable Gate Array (FPGA). In this article, a parallel timing synchronization architecture is proposed. In the architecture, a parallel First In First Out (FIFO) structure based on an index associated rearranging method, and a dual feedback loop based on the Gardner’s algorithm, are adopted. Taking advantages of the FIFO structure, 67% Look Up Table (LUT) is saved in comparison with earlier results, meanwhile the Numerically Controlled Oscillator (NCO) is efficiently improved to meet the FPGA timing requirements for real-time performance. MATLAB simulations are run to evaluate the Bit Error Rate (BER) deterioration of the architecture. The float- and fixed-point simulation results have shown that, The BER deteriorations are less than 0.5 dB and 1 dB, respectively. Further, the implementation of the architecture on a Xilinx XC7VX485T FPGA chip is achieved. A 20 giga bit per second (Gbps) 16 Quadrature Amplitude Modulation (16QAM) real-time system is achieved at the system clock of 159.524 MHz. This work opens a new pathway to improve the transmission capacity in real-time wireless communication systems.

Minimization of SIDELOBE Attenuation and Power of a Fir Low Pass Filter using FRFT and CSD Algorithm

For digital signal processing, communication systems and VLSI design architectures, an efficient FIR filter is required to eliminate the noise signals. To design an efficient FIR filter, the minimization of two parameters is required such as side lobe attenuation and power. These two parameters can be achieved by designing a FIR filter with the help of Fractional Fourier Transform (FrFT) and Canonical Signed digit (CSD) algorithm. In this work, Finite Impulse Response (FIR) low pass filter is designed by using both FrFT and ordinary Fourier Transform (FT) methods and their frequency responses are compared in terms of side lobe attenuation (SLA). After comparison of both methods, the better results are obtained for an FrFT based design of FIR low pass filter. Apart from this, the FrFT based design of FIR low pass filter is realized in direct form architecture and implemented in VLSI. Further, the Canonical Signed digit (CSD) algorithm is applied for the multiplication process in the architecture implementation to minimize the power consumption. Moreover, frequency response of FIR low pass filter is obtained by using MATLAB software and simulation and synthesis results are obtained by using Xilinx 13.1 ISE.

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a $16\times 16$ -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (−27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

Beyond 1 Tb/s Intra-Data Center Interconnect Technology: IM-DD OR Coherent?

We discuss technology options and challenges for scaling intra-datacenter interconnects beyond 1 Tb/s bandwidths, with focus on two possible approaches: pulse amplitude modulation (PAM)-based intensity modulation-direct detection (IM-DD) and baud-rate sampled coherent technology. In our studies, we compare the performance of various orders of PAM modulation (PAM4 to 8). In addition to these fixed PAM signaling options, a flexible PAM (FlexPAM) technique leveraging granularity in spectral efficiency (SE) is proposed to maximize link margin. For baud-rate sampled coherent technology, we propose a simplified digital signal processing (DSP) architecture to bring down power consumption of the coherent approach closer to that of IM-DD PAM. We also propose two new phase noise tolerant 2D coherent modulation formats to relax the laser linewidth requirement. In closing, a comparative study of fixed IM-DD PAM versus coherent polarization multiplexed-quadrature amplitude modulation (PM-QAM) is presented for a 1.6 Tb/s solution (200 Gb/s per dimension), with consideration of link loss/reach budget, power consumption, implementation complexity, as well as fan-out granularity.