Digital Signal Processing Filters Research Articles

Proposing A New Variable Window for Better Side Lobe Reduction

Digital signal processing is most widely used to process the signal. In digital signal processing filters are used to remove some unwanted constituents from aspired signal. Windowing is a scheme of finite impulse response filters. Present paper proposes a new versatile window function. It has two variable parameters first one is window span N and another changeable parameter is r. when the value of variable parameter r increases width of major lobe of window also increases with better side lobe reduction and vice versa. Gaussian window and Kaiser window are the well-known variable windows. This paper shows that the proposed window has more desirable results in comparison of Gaussian and Kaiser window with low power loss and better side lobe reduction. To achieve minimum power loss peak side lobe level should have to minimum. Proposed window has low peak side lobe level (-17.681dB) in comparison of Gaussian (-11.836dB) and Kaiser window (-6.9704dB). Proposed work shows that the proposed window has finer spectral characteristic then Gaussian and Kaiser window. FIR filter formed by applying proposed window has narrow -3dB bandwidth (2π×0.320 rad/sample) corresponding to FIR filter formed by using Gaussian and Kaiser window. Ripple ratio of FIR filter plotted by applying proposed window (-144.321dB) is less corresponding to FIR filter delineated by using Gaussian and Kaiser which indicates that the proposed window will give better side lobe rejection and reduce the aliasing problem. In the biomedical field noise present in ECG signal can also reduce by using proposed window.

Analysis of different digital filters for received signal strength indicator

Due to high demand in Internet of Things applications, researchers are exploring deeper alternative methods to provide efficiency in terms of application, energy, and cost among other factors. A frequently used technique is the Received Signal Strength Indicator value for different Internet of Things applications. It is imperative to investigate the digital signal filter for the Received Signal Strength Indicator readings to interpret it into more reliable data. A contrasting analysis of three different types of digital filters is presented in this paper, namely: Simple Moving Average filter, Alpha Trimmed Mean filter and Kalman filter. There are three criteria used to observe the performance of these digital filters which are noise reduction, data proximity and delays. Based on the criteria, the choice of digital signal processing filter can be determined in accordance with its implementations in [ractice. For example, Alpha-Trimmed Meanfilter is shown to be more efficient if used in the pre-processing of Received Signal Strength Indicator readings for physical intrusion detection due to its high data proximity. Hence, this paper illustrates the possibilities of the use of Received Signal Strength Indicator in different Internet of Things applications given a proper choice of digital signal processing filter.

Wavelet denoising and reconstruction of a microneedle embedded in human skin ex-vivo using terahertz pulsed reflectance.

Biological tissue can show promising features in the terahertz region of the electro-magnetic spectrum but face the problem that the signal to noise ratio can be poor due to the low energy output from the measurement instrument coupled with the high absorbance of water in biological tissue. Wavelet denoising and reconstruction are known to be suitable digital signal processing filters for reflected terahertz energy when appropriate thresholds, scales and mother-wavelets are chosen. In this article, we therefore describe a Wavelet transform-based method for denoising reflections of THz energy from ex-vivo human skin with an embedded microneedle. The wavelet reconstruction was then successfully used to identify the microneedle from the reflected waveform. This technique is potentially useful to enhance in-depth analysis and visualisation of underlying skin layers, lesions and penetration depth for targeted drug delivery.

Comparison of antenna dispersion and digital signal processing effects in ultrawideband Ground Penetrating Radar systems

Abstract In Ground Penetrating Radar it is of great interest to have a pulse width as narrow as possible to achieve best resolution capability. However, ultrawideband antennas may cause distortion to the radar signal due to dispersion, which is dependent on the frequency and bandwidth, as well as the direction of radiation. As dispersion causes an increase of the peak's width, the resolution capability is degraded. When frequency-based radar systems are utilized, such as stepped-frequency radar, a transformation of the recorded frequency-domain data to time domain is often required. There are different means of transformation at hand, the most popular being inverse Fourier Transform. Generally, such a transformation involves certain degrees of freedom in the processing of the data, which affect the appearance or even distort the resulting signal in time domain. In the same way, distortion may also be introduced to signals obtained by pulse radar, which is operating in time domain, when digital signal processing filters are applied to the time-domain data, modifying their frequency content. In contrast to dispersion these effects can be controlled — but not avoided. As an example, the typical sinc-shaped distortion of the time-domain signal after inverse Fourier Transform may be avoided by windowing of the frequency-domain data, a well-known basic technique in the digital signal processing domain. As dispersion, also windowing causes a broadening of the peak's width. However, this leads to the important question, to which degree both, dispersion and windowing, affect the time domain signal and which of them has more severe impact. In this paper we investigate both effects. We compare dispersion of different ultrawideband Vivaldi, Bowtie and Loaded Bowtie antennas with the ideal (theoretical) non-dispersive one. And we compare these results with the distortion effects introduced to the radar signal by windowing frequency-domain data prior to inverse Fourier Transform.

Hardware Implementation of DSP Filter on FPGAs

This paper describes the hardware implemention of Digital signal processing filters on FPGAs (Field programmable gate array). Traditionally, digital signal processing (DSP) algorithms are implemented using general purpose programmable DSP chips for low-rate applications. Alternatively, special purpose fixed function DSP chipsets and application specific integrated circuits (ASICs) are used for high-performance application. Technological amelioration by Xilinx on FPGAs in the past few years has opened new paths for engineers to design various applications on FPGAs. The FPGAs assert the high explicitness of the ASIC while avoiding its high development cost and its inability to accommodate design modifications after production. Highly adaptable and design-flexibility, FPGAs provide optimal device utilization through conservation of board space and system power important advantages not available with many stand-alone DSP chips.

VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

The need for a high-performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize the latest technique identified as oversampling systems. It was the most economical modulator and decimation in the communication system. It has been proven to increase the SNR and is used in many high-performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and it's VLSI implementation which was the sub-component in the oversampling technique. The design and realization of the main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half-band filters, and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted in power and area measurement on-chip core layout. The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308 x 0.308 mm2. It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.