Digital Signal Processor Core Research Articles

Hybrid Radix-16 Booth encoding and Rounding-based Approximate Karatsuba multiplier for Fast Fourier Transform computation in Biomedical signal processing Application

Multiplication is an essential biomedical signal processing function implemented in the Digital Signal Processing (DSP) cores. To enhance the speed, area and energy efficiency of DSP cores, approximate multiplication is used. Also, low power multiplier unit design is one of the requirements of DSP processor to meet the increasing demands. To balance both the design and error metrics of a multiplier design, an efficient Hybrid Radix-16 Booth Encoding and rounding-based approximate Karatsuba Multiplier (RBEKM-16) is proposed. This research introduces an Approximate Karatsuba multiplier based on rounding, utilizing rounding approximation to compute the least significant part of the product. Simple operators, like adders and multiplexers, replace complex and costly conventional Floating-Point (FP) multipliers in this process. Radix-4 logarithms are incorporated to further minimize hardware complexity and calculate the product's most significant part. Subsequently, an approximate 4-2 compressor is applied in the partial product reduction stage to generate the most significant bit result. In the experimental scenario, the efficiency of the multiplier is evaluated in terms of energy efficiency, area utilization and error rate by using Xilinx ISE 8.1i tool. The results from the experiments indicate that the suggested multiplier demonstrates improved energy efficiency, utilizes space more effectively, and performs well in applications related to biomedical signal processing. Further, the accomplished area utilization of the proposed 16-bit multiplier is 1068 , delay is 3.01 ns, power consumption is 0.021mW and power delay product is 119 fJ.

Exploring Handwritten Signature Image Features for Hardware Security

This paper presents a novel hardware security technique that leverages handwritten signature image features for securing intellectual property (IP) cores, such as digital signal processing (DSP) cores, against IP piracy and false claim of IP ownership threats. In our approach, an IP vendor's handwritten signature image features are first converted into a corresponding digital template, followed by mapping into hardware security constraints and implanting them into the design during high level synthesis (HLS) process. This paper presents methodologies of extracting feature set of a handwritten signature through sampling and of encoding of the samples into binary values using a tree based encoding, for generating the digital template. The results of the proposed approach are assessed in terms of strength of IP ownership proof, security against a forged signature and impact of embedding signature constraints on design cost. The results revealed that the proposed approach provides robust security at negligible design cost overhead and also outperforms state of the art hardware security approaches for DSP cores.

Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures

The Complex Matrix Multiplication (CMM) algorithm is known to require a high computing performance and presenting exceptional challenges in real-life applications. Recent advances in Very Long Instruction Word (VLIW) based Digital Signal Processors (DSP) demonstrated high computing capabilities with a very low power consumption. In this work, we propose three ultra-fast, parallel and efficient VLIW implementation approaches of the CMM algorithm which could be used to meet tighter real-time constraints of several signal and image processing applications like radars. A novel parallel kernel, task mapping strategy and low-level optimization techniques are suggested, to fit a set of modern VLIW architectures. Additionally, an original memory access management technique was adopted to accelerate the algorithm by avoiding cache misses and bank conflicts. The experimental results showed the effectiveness of the proposed approaches where a peak performance of 15.89 GFLOPS was achieved on one C66x DSP core with a core utilization of 99% and a speedup of about 1.61, 3 and 10 compared to the state-of-the-art, the most optimized vendor and the conventional approaches, respectively.

A Design Method for Low-cost and SOPC-based Flexible Lifting Control System

To efficiently reduce the development and production costs of the intelligent lifting control system, we introduce a design method for the intelligent lifting system with client-server architecture. We replace DSP processor core or DSP (Digital Signal processor) core with Nois II soft-core processor so that the design and production costs can be effectively cut. By replacing DSP processor or DSP processor core with Nois II soft-core processor, the design and production costs can be significantly reduced. In our design, loop vector control units work as a server processor, and a central computing unit with four independent multipliers and two adders is employed, with the implementation method based on a state machine. The experimental results prove effective in reducing resource requirements for FPGA (Field Programmable Gate Array), show that the proposed method can be successfully applied to the implementation of a complete intelligent flexible lifting control system on a low-end Altera Cyclone FPGA, and servo motor control achieves better dynamic performance

Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications

The approximate design has emerged as a revolutionary design paradigm to obtain energy efficient digital signal processing cores while exhibiting acceptable accuracy. In different signal processing architectures, multiplier is the prime arithmetic unit and significantly influences the performance of these cores. Therefore, four novel energy efficient rounding based approximate (RBA) multiplier architectures are proposed in this paper. These multipliers first approximate input operands to the nearest power of two values and then achieve multiplication using few adders and shifters. The proposed RBA multipliers significantly reduce implementation complexity and provide higher energy efficiency. Further, a novel reconfigurable rounding based approximate (RRBA) multiplier is proposed to achieve desired performance-quality tradeoff. Further, the performance of proposed RBA and RRBA multipliers is evaluated and analysed over the existing approximate multiplier architectures. The proposed 8-bit RBA0 requires 59.8% (54.7%) reduced area (delay) compared to the existing approximate multiplier. Finally, the efficacy of the proposed multipliers is demonstrated in the application by implementing Gaussian filters embedded with existing and proposed approximate multipliers. The Gaussian filter designed using RBA0 provides 32.5% reduced energy consumption over the filter with existing multiplier.

Impact of hardware steganography on DSP core datapath

The protection of Intellectual Property (IP) core for a Digital Signal Processing (DSP) kernel has become an important research area in the last few years for Consumer Electronics systems. The swelling threats of IP piracy, forgery, and counterfeiting and ownership abuse on DSP IP core are the principal reason behind that. This work investigates the impact of hardware steganography on protection of DSP IP core datapath against these threats. As a case study, the complete analysis of its impact on 8-point Discrete Cosine Transformation datapath architecture is presented.

Low‐cost robust anti‐removal logic for protecting functionally obfuscated DSP core against removal attack

Digital signal processing (DSP) cores (kernels) are key components of modern consumer electronics devices. However, protection of DSP kernels is very crucial considering its vulnerability to hardware threats such as reverse engineering (RE). Functional obfuscation is one of the security mechanisms which provide protection against RE. However, functional obfuscation logic is in itself vulnerable to removal attack. This Letter presents a novel anti-removal logic (ARL) unit which ensures protection against the removal attack on functional obfuscation logic. Further, the ARL unit is itself safeguarded against removal attack by incorporating design architecture customisation and camouflaging. Designer can customise and camouflage the internal gate structure network of the ARL blocks post-synthesis (post-mapping and fitting). The proposed ARL unit integrated with functionally obfuscated DSP design, yielded lightweight and highly secured solution against removal attack when compared to an existing approach. The proposed approach reported on an average 42.57% reduction in gate count and on an average 66.67% enhancement in security compared to a recent existing approach.

In brief

PAGE 372 A front-end adaptive folder with a filter is used to instantaneously push jammers to higher frequencies while preserving small signal integrity. Presented by a team of researchers from the USA, combinatorial intrinsic device characteristics are exploited to tune folding points and achieve maximum programmability. PAGE 396 A researcher from Japan has investigated the transmission characteristics of an optical signal which has been converted using detection, modulation and filtering from a high-speed terahertz-wave signal. The converted signal shaped with root Nyquist filters can be transmitted down a 9 km-long fiber without compensation. Received signals with jammer moved to gradually higher frequencies. PAGE 374 Digital signal processing cores are common in consumer electronics and require protection from the hardware threats posed by reverse engineering. A pair of researchers from India present a novel anti-removal logic unit which protects against attacks on functional obfuscation logic. The approach has significant security enhancements over current standards. Measured optical signal spectrum. PAGE 402 The energy storage battery in a microgrid can perform demand side management which requires a bidirectional power transmission control function with constant power. A group of Chinese researchers have designed a boost converter circuit topology followed by a timing trigger mechanism control system, with simulation demonstrating it achieves accurate power reference value tracking. Designer selected AND-OR network. PAGE 365 A pair of researchers from India propose a wideband circularly polarised antenna based on composite metamaterial structures applicable for small satellite applications. A new unit cell artificial magnetic conductor metasurface is used as a ground plane for the antenna which has increased bandwidth, gain and a wider axial ratio bandwidth despite its compact size. An operating mode of the proposed converter. Proposed metamaterial antenna front view.

An FPGA implementation of the matching pursuit algorithm for a compressed sensing enabled e-Health monitoring platform

Wireless monitoring of physiological signals is an evolving direction in personalized medicine and home-based e-Health systems. There are several constraints in designing such systems, with two of the most important being energy consumption and data compression. Compressed Sensing (CS) is an emerging data compression technique that can be used to overcome those constraints. This work presents a low-complexity CS hardware implementation on a Field-Programmable Gate Array (FPGA) for the reconstruction of compressively sensed signals using the matching pursuit (MP) algorithm, targeting health-care applications. The proposed hardware design is based on pipeline optimization of the Programmable Logic (PL) implementation performed on the Zynq FPGA, which provides a significant performance enhancement, namely an increased processing speed and a reduced computational time since it is 115x faster than the Matlab implementation and 75x faster than the Processing System (PS) implementation carried out on the same Zynq FPGA device, while achieving alternative a high-quality signal recovery with a Peak Signal to Noise Ratio (PSNR) of 23.8 dB. Comparisons against other state-of-the-art methods showed that the low complexity of the MP algorithm can be exploited for providing almost similar results to more complex algorithms using 87–583 less Digital Signal Processor (DSP) cores, 28–540 less Block RAMs and 10,300 to 84,700 less Look-Up Table (LUT) slices.

An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors

Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core embedded processors in SRAM-based FPGAs by using characteristics such as low utilization and fragmented accessibility of comprising units. To this end, we integrate the low utilized functional units into efficiently designed look-up table (LUT)-based reconfigurable units (RUs). To further improve the efficiency of the proposed architecture, we used a set of efficient configurable hard logics that implement frequent Boolean functions while the other functions will still be employed by LUTs. We have evaluated effectiveness of the proposed architecture by implementing the Berkeley RISC-V processor and running MiBench benchmarks. We have also examined the applicability of the proposed architecture on an alternative open-source processor (i.e., LEON2) and a digital signal processing core. Experimental results show that the proposed architecture as compared to the conventional LUT-based soft-core processors improves area footprint, static power, energy consumption, and total execution time by 30.7%, 32.5%, 36.9%, and 6.3%, respectively.

Fault-Tolerant DSP Core Datapath Against Omnidirectional Spatial Impact of SET

Fault due to the single-event transient (SET) on digital signal processing (DSP) cores has not been thoroughly studied in the research community. Moreover, as the technology scaling becomes more intense, the impact of transient fault now becomes visible both in temporal and spatial domains. Few techniques have been presented in the literature that simultaneously address temporal and the spatial effects of transient fault. However, none of these approaches consider the omnidirectional spatial propagation of transient fault. Furthermore, these approaches have failed to consider the impact of transient fault on switching elements. This calls for methodology to tackle both the temporal and omnidirectional spatial effects of the transient fault on DSP cores. The proposed approach tackles these issues and presents a novel methodology to generate a low-cost fault-tolerant DSP core datapath against temporal (kc-cycle) and omnidirectional spatial (km-unit) impacts of SET.

Robust Logic locking for Securing Reusable DSP Cores

A System on Chip (SoC) used in Consumer Electronics (CE) systems integrates a number of reusable Intellectual Property (IP) cores from digital signal processing (DSP), multimedia etc. However, these DSP based IP cores are susceptible to various hardware threats such as piracy, Trojan insertion, overbuilding and reverse engineering. Thus, security of DSP cores is very crucial. An IP core can be secured against aforementioned hardware threats by employing logic locking based security mechanisms. This paper presents a novel robust logic locking using hybrid locking cells for securing DSP cores. The proposed logic locking is based on a novel advanced encryption standard (AES) based reconfigurable hybrid locking cell architecture that ensures strong security against key sensitization, removal and SAT attacks. The strength of the proposed approach has been assessed in terms of probability of obtaining correct key of a locked design in exhaustive trials. Results of proposed work on DSP cores yielded higher logic locking strength and lower design overhead compared to recent prior works.

Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware

Digital signal processing (DSP) kernel-based intellectual property (IP) core forms an integral ingredient of consumer electronics devices. Thus, protection of these IP cores against reverse engineering attack is crucial. Functional obfuscation serves as a powerful mechanism to counter this hardware threat. However, functional obfuscation methodologies for DSP cores use security logics that are not lightweight and are prone to removal attack by an adversary. This paper presents a novel security mechanism for protecting functionally obfuscated DSP core against removal attack using low-cost, low-power key encryption hardware. The proposed methodology using lightweight secure hashing algorithm (SHA-512)-based key encryption custom hardware reconfigures the key-bits (resulting into structural reconfiguration) of the locking logic in a functionally obfuscated DSP design augmented with the complete logic synthesis of the design. This hinders the detection of the locking logic in the obfuscated design due to camouflaging. The proposed mechanism integrated with the functional obfuscation framework yielded lower power, lower gate count, and enhanced security compared with an existing approach. An average reduction of 25.86 % in gate count and power as well as the average enhancement of 43.75 % in security against removal attack was obtained in the proposed approach compared with a recent existing approach.

Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters

Digital signal processing (DSP) cores are integral components of consumer electronics (CE) devices. However, intellectual property (IP) cores suffer from the possibility of piracy, forgery, and fake ownership. To address these issues, this article presents the following: 1) a signature-free watermarking process for protecting DSP cores, 2) a covert, signature-free watermark that provides robust security at nominal overhead, and 3) a watermark detection process that can be demonstrated through a functional validation process.

Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation

Device aging is a critical failure mechanism in nanoscale designs. Prolonged device degradation may result in failure. Delay degradation of a design depends on various factors such as threshold voltage, temperature, input vector pattern and so on. An attacker who is aware of this phenomenon may exploit by accelerating the performance degradation mechanism. This study proposes a novel reliability and threat analysis of negative bias temperature instability (NBTI) stress on digital signal processing (DSP) cores. The main contributions of this study are as follows: (a) identifying input vectors that cause maximum degradation of DSP cores due to NBTI stress, (b) analysing impact of NBTI stress for varying stress time on DSP core in terms of delay degradation and (c) analysing performance comparison of stress versus no-stress condition for various input vector samples.

Optimizing DSP Cores Using Design Transformation [Hardware Matters

Reusable digital signal processing (DSP) intellectual property (IP) cores play a crucial role in numerous domains, including consumer electronics. However, optimizing DSP cores is crucial for the reduction of design area, delay, power, and so forth [1], [2]. Though several optimization techniques using evolutionary algorithms have been proposed, they incur design overhead and exploration time [1], [2].

Real-Time Object Tracking on a Drone With Multi-Inertial Sensing Data

Real-time object tracking on a drone under a dynamic environment has been a challenging issue for many years, with existing approaches using off-line calculation or powerful computation units on board. This paper presents a new lightweight real-time onboard object tracking approach with multi-inertial sensing data, wherein a highly energy-efficient drone is built based on the Snapdragon flight board of Qualcomm. The flight board uses a digital signal processor core of the Snapdragon 801 processor to realize PX4 autopilot, an open-source autopilot system oriented toward inexpensive autonomous aircraft. It also uses an ARM core to realize Linux, robot operating systems, open-source computer vision library, and related algorithms. A lightweight moving object detection algorithm is proposed that extracts feature points in the video frame using the oriented FAST and rotated binary robust independent elementary features algorithm and adapts a local difference binary algorithm to construct the image binary descriptors. The K-nearest neighbor method is then used to match the image descriptors. Finally, an object tracking method is proposed that fuses inertial measurement unit data, global positioning system data, and the moving object detection results to calculate the relative position between coordinate systems of the object and the drone. All the algorithms are run on the Qualcomm platform in real time. Experimental results demonstrate the superior performance of our method over the state-of-the-art visual tracking method.

Towards real-time crops surveillance for disease classification: exploiting parallelism in computer vision

Considering the incessantly increasing economic losses due to plant diseases in the agricultural sector, we have designed a real-time system capable of classifying plant diseases. In this context, we have proposed an image processing algorithm that transforms the image into three colorspaces, which are processed simultaneously. The algorithm executes in a series of intermediate steps, including contrast stretching, feature vector construction, and identification of salient regions. To enable effective execution, we have also proposed the underlying On-Chip communication architecture that allows efficient interconnection between the three digital signal processing cores, each processing its own colorspace. The architecture has been synthesized for 90 nm process, as well as on an FPGA, achieving a post-layout operational frequency of 644 MHz, and an area of 1208.9 µm2 on the die. We demonstrate that our system outperforms few existing works in literature in terms of accuracy and computation time.

Hybrid control of the dc–dc SRC operating below resonance

Control and stabilisation of the resonant converters are essential problems in power electronics. The conventional model of the dc–dc series resonant converter (SRC) is derived using the sinusoidal approximation and generalised averaging followed by linearisation about an operating point. This model involves considerable approximation and is not applicable for large variation of load and supply voltage. The authors have already proposed a direct piece-wise affine (DPWA) modelling and control approach for the SRC that operates above resonant frequency. However, the DPWA technique is not applicable to an SRC that operates below resonance because of the presence of harmonics. In this study, a dynamic voltage-controlled oscillator (VCO) is introduced, so that the overall system consisting of the proposed VCO following by the SRC is modelled as a PWA system. Then, a hybrid controller is designed in order to regulate the dc output voltage of the SRC operating below resonance. Also, the stability analysis of the closed-loop system is presented in the form of linear matrix inequalities. A prototype of the SRC is constructed and the proposed hybrid controller is implemented on a digital signal processor (DSP) core. The simulation and experimental results show the effectiveness of this modelling and control approach.

Design and test of a new development FPGA board for mobile robot research

This paper presents the design and testing of a newly developed field programmable gate array (FPGA) board for mobile robot research. The idea consists of interfacing the FPGA to a 16-bit digital signal controller (dsPIC). This idea enables the FPGA designs to communicate with the dsPIC through the integration of per-written driver modules to be used in a wide variety of digital and analog peripheral modules. It also allows the use of a high-performance digital signal processing core in many signal processing-based mobile robot applications. The proposed FPGA board allows users to develop, test, and deploy quick and cost-effective complete design solutions to control the entire robot system in various applications without the need for external components.