Digital Signal Processing Chip Research Articles

Design and DSP-chip implementation of a novel bilinear-LDI digital Jaumann filter

The design and implementation, on a digital signal processing (DSP) chip, of a novel high-quality recursive digital filter is presented. The proposed digital filter is derived from an equally resistively terminated lossless Jaumann two-port network by using the bilinear-LDI (bilinear lossless discrete integrator) design technique. It has the important practical property that all the inductor-based states can be computed simultaneously and all the capacitor-based states can be computed simultaneously, thereby permitting a fast parallel-processing speed which is virtually independent of the order of the filter. This digital filter can be made minimal in the number of multipliers, requiring n multipliers for the realization of lowpass and bandpass filters, and n+1 multipliers for the realization of highpass and bandstop filters, where n is the order of the continuous-time prototype reference filter. It is shown that when implemented using modern DSP chips, such a filter exhibits very high-quality performance characteristics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

DSP beamforming and talker tracking with a linear microphone array

One of the problems for all speech input is the necessity for the talker to be encumbered by a head‐mounted, hand‐held, or fixed position microphone. An intelligent, electronically aimed undirectional microphone would overcome this problem. Array techniques hold the best promise to bring such a system to practicality, although the acoustic problems are manifold. High‐speed digital signal processing (DSP) chips have made it possible to attack the essential problems of forming the beam, aiming the microphone, and tracking a unique talker. A useful beamforming algorithm and a two‐step talker‐tracking algorithm are introduced. In the latter, step 1 is a rather conventional filtered cross‐correlation method; the delay between some pair of microphones is determined to high accuracy using interpolation on the sampled data. Then, using the fact that the delays for a point source should fit a hyperbola, a best hyperbolic fit is obtained using nonlinear optimization. Results indicate that this method works reliably for signal‐to‐noise ratios of less than 10 dB. [This work principally supported by NSF Grant No. MIP‐8809742 and DARPA/NSF Grant No. IRI‐8901882.]

Models of speech and hearing and their applications: Overview and outlook

Electronic speech coding had its origin in 1928 when Homer Dudley proposed to send speech signals over a new transatlantic telegraph cable with the (then) enormous bandwidth of 100 Hz. Dudley argued that speech was generated by slowly moving articulators and should therefore require only some 100-Hz total bandwidth for transmission. Since extraction of these parameters proved difficult, Dudley suggested, as an alternative, the transmission of the likewise slowly changing spectral information. The result was the channel vocoder, which (together with formant and voice-excited vocoders) dominated speech coding and that of musical sounds of single-pitch instruments until the mid 1960s. Unhappy with the vocoder's “electronic accent.” Bishnu Atal and the author, in 1967, advanced the idea of linear predictive coding (LPC), motivated by the desire to replace rigid vocoderlike coding by a more flexible method in which a “prediction residual” could represent deviations of real speech signals from an assumed all-pole model. In 1972, subjective error criteria were introduced, based on auditory models of masking and the possibility of “hiding” quantizing noise under the speech signal. The resulting code-excited linear predictive (CELP) coders based on statistical models have been operated at 1/4 bit per sample for the residual at virtually no audible degradation. With powerful digital signal processing chips, CELP has now become the method of choice for synthetic-voice applications. For musical sounds, masking models and linear predictive coding, which is equivalent to prewhitening of the spectrum, lead to a substantial reduction in the required number of bits per sample.

An evaluation of Radon transform computations using DSP chips

The Radon transform and its inverse (a filtered backprojection) are receiving increasing attention for applications in image reconstruction. As data collection capabilities and image reconstruction algorithms have become more sophisticated, the computational intensity of these problems has drastically increased. Parallel processing techniques are being used to implement highspeed hardware designs that will speed up this computationally burdensome task. Parallel arrays of digital signal processing (DSP) chips may be used to compute the Radon transform and back-projection for high-speed image reconstruction. In this paper we describe computation of the Radon transform and back-projection using a parallel pipelined processor architecture of DSP chips and evaluate the accuracy of the computations and quality of reconstructed images. To justify the computational approach selected, alternative procedures for computation of the Radon transform and back-projection are described and their performance using the 32-bit fixed-point arithmetic of the selected DSP chips are compared. We present, evaluate, and compare the simulated performances of implementations of these procedures on two fixed-point DSP chips: the TI TMS32020 and the AT&T DSP16.

Evaluation of real time adaptive noise cancelling algorithms as implemented using a digital signal processor chip

Adaptive lattice noise cancelling algorithms have features that make them appear attractive for the realisation of realtime adaptive noise cancellers with single chip digital signal processors. Two popular adaptive lattice noise cancelling algorithms have been evaluated for this application. Considered are stochastic gradient lattice and least squares lattice algorithms. For the purpose of comparison, the stochastic gradient transversal algorithm is also evaluated. Their performances under a variety of signal and noise excitations are summarised and compared in terms of operating rates and misadjustments.

A 5-V front-end chip for a universal voice-band modem

A monolithic circuit designed for a 5-V, 1.2- mu m CMOS process combining a full analog front end with all of the logic functions that, along with one or two external digital signal processor (DSP) chips, can implement all of the voice-band modem standards from 300 to 14400 b/s is described. The analog portion of the circuit occupies 23 kmil/sup 2/ (14.9 mm/sup 2/). Combined with roughly 6000 gates of random logic, I/O pads, and supply buses, the die area totals 63 kmil/sup 2/ (40.7 mm/sup 2/). By being designed for operation with a single 5-V supply, analog circuits may use current high-density processes and migrate to future denser processes. Although analog circuitry will not scale as fast as digital circuitry, performance levels can be maintained. This circuit illustrates the potential for combining high-performance analog functions with complex digital functions on a single VLSI chip, using high-density processes. >

A speech synthesizer for Mandarin Chinese

The design and implementation of a linear predictive coding (LPC) speech synthesizer using a general-purpose floating-point 32-bit digital signal processing (DSP) chip for Mandarin Chinese are described. The hardware synthesizer board consists of a plug-in card which can be installed in a personal computer (PC). The software consists of a hand-optimized DSP assembly program which can be downloaded from the host PC to the synthesizer RAM for real-time speech synthesis. Computer programs in Pascal have also been developed to extract the ten reflection coefficients, pitch, and gain values for the LPC synthesizer. A database of LPC parameters comprising the 56 Mandarin phonemes and the four standard pitch contours corresponding to the four lexical tones of monosyllabic Mandarin has also been created for the synthesizer. >

Dual-processor controller with vehicle suspension applications

A dual-processor controller suitable for computation-intensive control and signal-processing algorithms is described. The controller is built around a general-purpose microcontroller and a digital signal processor (DSP). The main goal of the design is efficient computation of mathematically oriented algorithms with the ability to interface with sensors and actuators. The effectiveness of controllers incorporating DSP chips is demonstrated with two applications of suspension-sensor data frequency-domain analysis and state estimation of a quarter-car suspension test rig. >

Intelligent guidance for headway and lane control

The principal objective of this study is to define techniques for using graphical imagery alone as guidance information for automotive headway and lane control. The goal is to accelerate, steer, and brake an automobile at normal speeds on both limited-access and conventional highways, including entry/exit ramps, multiple-lane roads, and undivided highways, and accounting for mixed traffic, road signs, traffic signals, and unexpected emergencies. It is expected that a system capable of performing these tasks would consist of one or more television cameras, pattern-recognition logic implemented in digital signal processing chips, a rule-based expert system for guidance and control, conventional motion sensors, and actuators for steering, braking, and throttle control.

DSP-Based Multipurpose Instrumentation

The paper illustrates the development of low cost multichannel digital instrumentation for real-time control applications. The realization is based on the use of an advanced digital signal processing chip, providing the necessary computing power and processing throughput. Algorithms perform Discrete Fourier Transform spectral analysis of the incoming signals and further process data to compensate for the effects of spectral leakage. A variety of parameters can be obtained with good accuracy from the knowledge of signal spectra simply by adopting different computing routines. The application of a two channel instrument in the monitoring of electrical power under nonsinusoidal conditions is considered, and results are given for the case of linear loads. Absolute measurement errors are of the order of 10-4-10-5, while a sampling rate in excess of 200kHz per channel is achieved.The structure of the instrument is very simple, and only standard devices are needed to realize it. As a result, it is well suited as a low cost and flexible measurement block in control systems.

Reduced-complexity stochastically-excited coder for the low bit-rate coding of speech

Stochastically-excited linear predictive (STLP) coders recently proposed in the literature can produce good quality speech at 4·8 kbits-1. However, these coders suffer from the problem of extremely high computational complexity. As a result, it is not possible to implement these coders on a single digital signal processor (DSP) chip. In the present paper, a new two-stage method is proposed for reducing the computational complexity of the STLP coder. This method can reduce the computational load of the STLP coder by a factor of 25 without sacrificing the quality of the synthetic speech. When this method is used in conjunction with the transform-domain filtering method of Transcoso and Atal, the computational requirement of the STLP coder reduces to 0·35 million multiplications per second, which can easily be met by a present-generation single DSP chip.

Implementation of a self-tuning controller using digital signal processor chips

Implementation aspects of a self-tuning motion controller, which uses the Texas Instruments TMS32010 digital signal processor (DSP) chip, are described. The potential advantages in using a DSP chip include reduction in operation time, development time, and cost. The self-tuning controller can track variations in system parameters as well as system disturbances. Algorithms are described, experimental results are presented, and implementation strategies to overcome limitations of such systems are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analog speech scrambling system using the FFT technique with high-level security

A full-duplex analog speech-scrambling system is proposed for application to mobile communication systems and public switched telephone networks. The scrambling algorithm is based on the rearrangement of the fast Fourier transform (FFT) coefficients accompanied by adaptive dummy spectrum insertion and companding operation. The simulation results indicate that the scrambled speech has no residual intelligibility and the descrambled speech quality is satisfactory. The hardware unit is implemented by using seven advanced digital signal processor chips, including those for an adaptive equalizer and an echo canceller for full-duplex operation. The performance is proven to be satisfactory. >

The architectures and design of a 20-MHz real-time DSP chip set

A set of four real-time 20-MHz digital signal processor (DSP) chips has been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video line delay. The circuits were implemented in a 1.5- mu m CMOS process and are fully functional with a 20-MHz clock rate. The processors have reconfigurable windows to allow processing on both one-dimensional and two-dimensional data. The FIR filters can be used in multiprocessor systems to increase the window size and the data precision.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A real-time adaptive lattice predictor using a digital signal processor chip

A real-time adaptive lattice predictor was implemented using a digital signal processing chip. The implementation comprises input-output units, a central processing and control unit, and supporting software. The performance of the hardware was verified by comparing an input signal and the one-step prediction signal calculated by the predictor. The maximum operating frequency for the four-stage lattice structure was 13.5 kHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Interprocessor communication in synchronous multiprocessor digital signal processing chips

The authors discuss interprocessor communication in synchronous multiprocessor DSP (digital signal processing) chips, the types of systems that are synthesized by the Cathedral II silicon compiler. A model for the data flow between two processors is presented. A number of architectural possibilities are discussed. Key concepts are a double-buffered memory cell and an extended method of pointer addressing. This method leads to the definition of 'once in, once out' communication, as opposed to conventional FIFO (first in, first out) buffering. The minimization of the buffer size by skewing the operation of the processors is worked out for specific important types of communication. The proposed techniques have been implemented in a synthesis tool which is part of Cathedral II. The practical significance of the work is illustrated with several examples. >

A digital color CCD imaging system using custom VLSI circuits

The authors describe a prototype digital imaging system that can be configured as a single-sensor video camera or a film-to-video converter. The system includes a CCD (charge-coupled device) image sensor with a 3G color filter pattern, two full-custom CMOS digital video signal processing chips, and a custom electronically programmable sequencer chip. The CMOS VLSI digital circuits offer real-time operation while meeting the size, power, and cost constraints of one-chip cameras and fill-to-video converters. System timing and design methodology are discussed. >

Digidesign's Sound Accelerator: Lessons Lived and Learned

This paper describes Digidesign's Sound Accelerator, a digital signal processing card for the Apple Macintosh II and SE based on Motorola's 56001 digital signal processing (DSP) chip. The card also includes dual 16-bit digital-to-analog converters allowing 44.1 KHz stereo playback. An expansion port on the card provides connection to a stereo 16-bit analog-to-digital conversion box as well as an Audio Engineering Society/European Broadcast Union (AES/EBU) digital interface for digital audio tape (DAT) or compact disk (CD) player interfacing. This paper describes the card's hardware and then outlines the development environment that has been created for the Sound Accelerator. Finally, there is a discussion of the limits of this environ-

A real-time autoregressive spectrum analyzer for Doppler ultrasound signals

A system based on a digital signal processor and a microcomputer has been programmed to estimate the maximum entropy autoregressive (AR) power spectrum of ultrasonic Doppler shift signals and display the results in the form of a sonogram in real-time on a computer screen. The system, which is based on a TMS 320C25 digital signal processor chip, calculates spectra with 128 frequency components from 64 samples of the Doppler signal. The samples are collected at a programmable rate of up to 40.96 kHz, and the computation of each spectrum takes typically 3.2 ms. The feasibility of on-line AR spectral estimation makes this type of analysis an attractive alternative to the more conventional fast Fourier transform approach to the analysis of Doppler ultrasound signals.

A digital signal processor for an ANSI standard ISDN transceiver

The digital signal processing chip of a two-chip ISDN (integrated services digital network) basic access transceiver based on the ANSI standard 2B1Q code is described. Nonlinear echo cancellation is used to improve the loop coverage. The chip features a multiprocessor architecture, where each processor is optimized for the algorithm used. Full observability of internal signals and adaptive filter coefficients is supported. The device is fabricated in a 1.25- mu m double-level-metal CMOS process with an active area of 47 mm/sup 2/. >