Digital Self-calibration Technique Research Articles

A low power and small area digital self-calibration technique for pipeline ADC

A digital self-calibration implementation with discontinuity-error and gain-error corrections for a pipeline analog-to-digital converter (ADC) is presented. In the proposed calibration method, the error owing to each reference unit capacitor of the multiplying D/A converter is measured separately using a calibration capacitor and an enhanced resolution back-end pipeline ADC acting as an error quantizer. The offset and finite open loop DC-gain of the operational amplifier and capacitor mismatches, the reference voltage mismatch can all be calibrated. The calibration can be achieved by that only used addition and subtraction. Hence, it needs low power and area consuming. A prototype ADC with the proposed calibration was fabricated on a 0.5μm double-poly triple-metal CMOS process. The power consumption and area of the calibration circuit are only 10.1mW and 1.05mm2, respectively. At a sampling rate of 30MS/s, the calibration improves the DNL and INL from 2.59 LSB and 14.98 LSB to 0.72 LSB and 1.82 LSB, respectively. For a 1.25MHz sinusoidal signal, the calibration improves the signal-to-noise-distortion ratio and spurious-free dynamic range from 43.1dB and 52.1dB to 75.51dB and 83.61dB, respectively. The 12.25 effective number of bits at 30MS/s ADC consumes a total power of 136mW.

Digital foreground calibration of capacitor mismatch for SAR ADCs

A foreground digital self-calibration technique that improves capacitor matching of a digital-to-analogue converter (DAC) employed in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. By exploiting an antisymmetric behaviour of capacitor mismatch errors in SAR ADCs and the proposed DAC switching scheme, the calibration technique significantly reduces capacitor mismatch errors without resorting to extensive computation or dedicated circuits.

Self-Calibration Techniques of Pipeline ADCs Using Cyclic Configuration

This paper proposes a digital self-calibration technique for pipelined ADC. In this technique, the pipelined ADC is composed of a series of cyclic ADCs and each stage has independent digital self-calibration. Because of this, our technique achieves higher accuracy calibration than the conventional method that calibrates by using later stages. Applying the proposed method, we simulated the pipelined ADC with MATLAB and showed that higher accuracy calibration can be achieved with a smaller number of pipeline stages.

Digital self-calibration technique based on 14-bit SAR ADC

An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter (SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.

An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth

A spread-spectrum clock generator (SSCG) is realized by an under-damping all-digital phase-locked loop (PLL). In this SSCG, the spread-spectrum clocking is achieved by switching the divider without a delta-sigma modulator. By using a digital self-calibration technique, the frequency of this SSCG has a triangular modulation profile and relaxes the process variations. This SSCG is fabricated in a 0.18 μm CMOS process. The measured electro-magnetic interference reduction is 14.37 dB. The measured rms and peak-to-peak jitters are 1.49 ps and 13.33 ps in a PLL mode, respectively. The measured rms and peak-to-peak jitters are 2.67 ps and 19.90 ps in a spread-spectrum modulation, respectively.