Digital RF Processor Research Articles

Built-In Measurements in Low-Cost Digital-RF Transceivers

Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRPTM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as ‘soft specifications’, are defined.

An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter

A new linearization scheme is proposed, which compensates for nonlinear distortions experienced in the amplitude-modulation path of a digital polar EDGE transmitter integrated in a 65-nm CMOS transceiver system-on-chip (SoC) based on the Digital RF Processor (DRP) technology. The measured amplitude and phase distortions are stored in lookup tables and used for predistortion without requiring inversion computations, thus achieving significant complexity reduction. Adaptive linear interpolation along with adaptive resolution enhancement provides the desired performance across power levels. With the presented scheme, the transmitter's measured performance significantly exceeds the EDGE specifications with an error vector magnitude (EVM) of typically 3% and a close-in modulated spectrum of -64 dB at a 400-kHz offset from the carrier frequency.

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> ) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.

A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers

A novel approach for mitigation of self-interference in highly-integrated wireless transceivers is presented. Several examples of possible applications of this approach in a wireless cellular transceiver system-on-chip (SoC) are listed, and the application of one example is presented in detail. Mathematical analysis, simulation results, measurements, and implementation details are provided for the demonstrated technique, which was designed to minimize jitter induced onto the reference clock of a GSM transceiver's PLL. Excessive jitter on this clock, caused by multiple RF aggressors centered at harmonics of it, creates amplified in-band phase-noise at the RF output of the PLL, resulting in failures in the transmitter's performance. The identification of this highly complex interference mechanism, which represents a significant part of this work, is discussed in detail, as is the implemented solution. The presented phase-adjustment technique, leveraging specific features of the digitally intensive PLL and available digital-signal-processing resources, is demonstrated in a GSM system-on-chip (SoC) based on the Digital RF Processor (DRPtrade) technology in 90 nm CMOS. As it does not involve dedicated hardware, nor does it noticeably increase the current consumption, it represents a cost-free solution in the final product.

SSCS-Taipei Offers Short Course on CMOS Single-Chip Radio Design, Programs in Hsinchu and Taipei Funded by SSCS Extra Chapter Subsidy

Programs in Hsinchu and Taipei Funded by SSCS Extra Chapter Subsidy Approximately 80 participants attended a two-day course sponsored by SSCS-Taipei at National Chiao-Tung University in Hsinchu and at National Taiwan University, Taipei on August 20 and 21, 2008, respectively. The presentations by Dr. Bogdan Staszewski of Texas Instruments entitled "Digital RF Processor (DRPTM) for Single-chip Mobile Radios: All-digital PLL, Transmitter and Discrete-time Receiver" were made possible by an SSCS chapter subsidy. lost this piece, recaptureonline

Verification of Digital RF Processors: RF, Analog, Baseband, and Software

Single-chip RF SoCs are seeing widespread acceptance in wireless applications. In this paper we address the issue of design verification of single-chip RF SOCs in a framework that accepts RF input and analyzes receiver BER performance and transmitter output distortion and phase noise by processing several thousand packets of baseband information while compensation algorithms are simultaneously executed. No comprehensive methodology exists to date for designing such complex systems. This paper present a novel approach that allows building complex RF SoC systems based on VHDL modeling and simulation and opens up major avenues of model development for RF and analog circuits. This approach has been successfully applied to verify two generations of digital RF processors (DRP) in deep-submicron technologies

RF Built-in Self Test of a Wireless Transmitter

RF frequency synthesizers and transmitters for wireless system-on-chips have recently migrated to low-cost deep-submicrometer CMOS processes that facilitate all-digital implementations. In addition to all the benefits of lower power, lower silicon cost, reduced board area, and improved performance that the scaled CMOS integration entails, the testing costs for RF performance and wireless standard compliance could also be drastically reduced. In this brief, we propose a built-in self test (BIST) method, which is based on the premise that the internal frequency synthesizer and transmitter signals are in digital format allowing for digital signal processing to ascertain the RF performance without external test equipment. With the RF BIST capability, millions of SoCs can be calibrated and tested in a production environment using a low cost digital tester while benefiting from increased test coverage and reduced test time and cost. The presented techniques have been successfully implemented in two generations of commercial digital RF processors: 130-nm Bluetooth and 90-nm GSM single-chip radios

Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers

RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digitally intensive domain for a wireless RF transceiver, so that it enjoys benefits of digital and switched-capacitor approaches. Direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio. We further present details of the RF receiver front end for a GSM radio realized in a 90-nm digital CMOS technology. The circuit consisting of low-noise amplifier, transconductance amplifier, and switching mixer offers 32.5 dB dynamic range with digitally configurable voltage gain of 40 dB down to 7.5dB. A series of decimation and discrete-time filtering follows the mixer and performs a highly linear second-order lowpass filtering to reject close-in interferers. The front-end gains can be configured with an automatic gain control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations. Even under the digital switching activity, noise figure at the 40 dB maximum gain is 1.8 dB and +50 dBm IIP2 at the 34 dB gain. The variation of the input matching versus multiple gains is less than 1 dB. The circuit in total occupies 3.1 mm2 . The LNA, TA, and mixer consume less than 15.3 mA at a supply voltage of 1.4 V.

Digital RF processing: toward low-cost reconfigurable radios

RF circuits for multi-gigahertz frequencies have recently migrated to state-of-the-art low-cost digital CMOS processes. This article visits fundamental techniques recently developed that migrate RF and analog design complexity to the digital domain for a wireless RF transceiver. All-digital phase locked loop and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. Software layers are defined to enable these architectures to develop an efficient software-defined radio. The ideas presented have been used to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.