Digital Readout Circuit Research Articles

A 3216 μm2 MOS-Based Temperature Sensor with a Wide Temperature Measurement Range and Linear Readout

This paper introduces an MOS-based intelligent temperature sensor with a linear readout. Compared with similar designs, the proposed sensor utilizes the DIBL effect to reduce the precision requirement for the voltage reference source and compensate for the temperature measurement range. A compact voltage reference circuit is introduced, which generates two reference voltage bases using only three transistors. In addition, the proposed digital readout circuit does not require a subtractor or a divider, further saving area. Fabricated in a 55 nm CMOS process, the proposed sensor occupies a compact area of 3216 μm2. Post-simulation results show it has a maximum error of −0.52/+0.28 °C within the temperature range of −20 °C to 120 °C after two-point calibration. The power supply voltage range of the sensor is 0.8 to 1.8 V. It has a maximum voltage sensitivity of 5.7 °C/V and its power consumption is only 166 nW, with a power supply voltage of 0.8 V.

A simple digital readout circuit for differential resistive or capacitive sensors

This paper introduces and analyzes a novel direct interface circuit (DIC) that directly connects differential resistive and capacitive sensors to digital processors (DPs), performing a magnitude-to-time-to-digital conversion of the information they provide. The simple circuit performs the readout using two passive components, the differential sensor and the DP. In some cases, the circuit may require an additional passive element. The DP only uses common digital resources such as bidirectional pins or a counter, meaning microcontrollers, FPGAs, or ASICs could all be used as DPs. Different DICs proposed in the literature for reading differential sensors require three time measurement processes to estimate the variable to be measured. The new circuit requires only one, saving time and energy dissipation and reducing the number of error sources. A design based on an FPGA has been implemented as a proof of concept. Measurement times in the order of 1.1–1.3 ms have been obtained with this configuration. Errors in the readout of a differential resistive sensor are below 0.34% in the worst case and below 0.63% for a differential capacitive sensor.

Digital Tri-Axis Accelerometer with X/Y-Axial Resonators and Z-Axial Capacitive Seesaw.

A tri-axis accelerometer with a digital readout circuit and communication system is introduced. It is composed of two resonant accelerometers in the x and y-axis, and a seesaw capacitive one in the z-axis. The device is encapsulated in air to ensure that the z-axis works in an over-damped state. Moreover, the closed-loop drive circuit establishes the x-axis and y-axis in resonant mode, and the z-axis in force balance mode. A miniaturized measurement based on FPGA is designed to collect these output signals. The phase noise of the resonance part and the amplitude noise of the seesaw part are studied by simulation. The model can predict the contribution of each part to the measurement error and Allan variance. Multiplied clock and Kalman filter in sliding window are used to reduce the frequency error. The test results show that the accelerometer has low bias instability (<30 μg), low cross-coupling error (<0.5%), and low nonlinearity (<0.1%). The tri-axis digital accelerometer with serial ports is more valuable than the previous works with large commercial instruments.

Study of Residual-time-counting Pulse Frequency Modulation Digital Readout Circuit for Ingaas Focal Plane Array

Study of Residual-time-counting Pulse Frequency Modulation Digital Readout Circuit for Ingaas Focal Plane Array

A High-Sensitivity and Low-Power Circuit for the Measurement of Abnormal Blood Cell Levels

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter-Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65-nm CMOS technology and post-layout simulations show 15.25-aF sensitivity. The total circuit occupies 2,184-[Formula: see text]m2 silicon area and consumes 216[Formula: see text][Formula: see text]A from a 1-V power supply.

Digital Time-Division Multiplexing Readout Circuit for Sensor Arrays

We have devised a digital time-division multiplexing (TDM) scheme for minimizing the circuit complexity required for an array of sensors. As a proof-of-concept, we have designed, fabricated, and tested a four-channel digital TDM readout circuit. The proposed scheme can be generalized for a larger number of channels. The readout circuit comprises an array of ADCs to digitize sensor outputs, a multiplexing unit, a clock controller, and a counter with parallel-to-serial output interface. For demonstration purposes, we employed low-pass phase modulation–demodulation ADCs running in a synchronous mode of operation. To facilitate an independent verification of circuit operation, we also placed an on-chip pattern generator to apply a unique pattern to each channel. The multiplexing unit is based on an array of sequentially triggered switches, each controlling the flow of data from a single ADC to a common output bus. In our scheme, the switches are realized using RS-flip-flops with nondestructive (RSN) readout cells with only one RSN cell turned on at a time. Multiplexed output data were stored in ripple counter based on T-flip-flops and read out to room temperature electronics using a serial interface. The chip was immersed in liquid helium at 4.2-K temperature and extensively evaluated at sampling frequencies up to 12.8 GHz. By means of embedded pattern generators, we proved the correct operation of each channel and of all four channels combined. We also were able to perform reconstruction of a signal applied to individual ADC. The chip was fabricated using HYPRES’ 4.5-kA/cm2 process with four Nb metal layers. We briefly discuss the proposed scheme's scalability for higher current density and smaller feature size fab processes.

A Robust Capacitive Digital Read-Out Circuit for a Scalable Tactile Skin

This paper presents a robust, capacitive digital read-out circuit (ROC) for sensitive skin applications in humanoid robots. The ROC can be calibrated to null the parasitic effects of transducer variation due to physical assembly. A prototype is fabricated in a 130 nm RFCMOS process, with an active area of $221\times 79~\mu \text{m}^{2}$ and 1.84 $\mu W$ power consumption at $V_{\mathrm {DD}}=1.2\text{V}$ and 1ms read-out rate. The ROC output is robust to $V_{\mathrm {DD}}$ and temperature variations in a range ${|\Delta V_{\mathrm {DD}}|}\leq 20\%$ and (25–53) °C. Furthermore, it can provide up to 200m $V_{\mathrm {pp}}$ power supply sine wave rejection in the range 50Hz–5MHz at $V_{\mathrm {DD}}=1.1\text{V}$ , for an output standard deviation lower than one LSB. Owing to its features and its digital modularity, the ROC was co-designed with a scalable and modular Multi-Walled Carbon NanoTube (MW-CNT) Nano composite transducer, to achieve tunable output sensitivity by adjusting the sensor nominal capacitance and the reference capacitance. The maximum sensitivity of 5.23 fF per LSB was reached when both match. The ROC was then validated with the MW-CNT nanocomposite sensor which exhibits a piecewise behaviour. 5.3 and 7.1 ENOB were extrapolated in the low-load and medium-load regions, respectively. Besides the major advantage of tunable sensitivity, the presented ROC features the lowest acquisition time and one of the most compact sizes among the state-of-the-art ROCs. Moreover, process voltage and temperature (PVT) robust output and ultra-low power consumption make this solution very attractive to replicate human physiology at robotic-level.

A novel technology for measuring the eruption temperature of silicate lavas with remote sensing: Application to Io and other planets

The highly variable and unpredictable magnitude of thermal emission from evolving volcanic eruptions creates saturation problems for remote sensing instruments observing eruptions on Earth and on Io, the highly volcanic moon of Jupiter. For Io, it is desirable to determine the temperature of the erupting lavas as this measurement constrains lava composition. One method of determining lava eruption temperature is by measuring radiant flux at two or more wavelengths and fitting a blackbody thermal emission function. Only certain styles of volcanic activity are suitable, those where detectable thermal emission is from a restricted range of surface temperatures close to the eruption temperature. Volcanic processes where this occurs include large lava fountains; smaller lava fountains common in active lava lakes; and lava tube skylights. Problems that must be overcome to obtain usable data are: (1) the rapid cooling of the lava between data acquisitions at different wavelengths, (2) the unknown magnitude of thermal emission, which has often led to detector saturation, and (3) thermal emission changing on a shorter timescale than the observation integration time. We can overcome these problems by using the HOT-BIRD detector and a novel, advanced digital readout circuit (D-ROIC) to achieve a wide dynamic range sufficient to image lava on Io without saturating. We have created an instrument model that allows various instrument parameters (including mirror diameter, number of signal splits, exposure duration, filter band pass, and optics transmissivity) to be tested to determine the detectability of thermal sources on Io's surface. We find that a short-wavelength infrared instrument on an Io flyby mission can achieve simultaneity of observations by splitting the incoming signal for all relevant eruption processes and still obtain data fast enough to remove uncertainties in accurate determination of the highest lava surface temperatures. Observations at 1 and 1.5μm are sufficient for this purpose. Even with a ten-way beam split, instrument throughput generates acceptable signal-to-noise values. Accurate constraints on lava eruption temperature are also possible with a visible wavelength detector so long as data at different wavelengths are obtained simultaneously and integration time is very short. Fast integration times are important for examining the thermal emission from lava tube skylights due to rapidly changing viewing geometry during close flybys. The technology described here is applicable to instruments observing terrestrial volcanism and for investigating proposed volcanic activity on Venus, where lava composition is not known.

Measuring the Mutual Effects of a CZT Detector and a 3T MRI for the Development of a Simultaneous MBI/MRI Insert

A cadmium zinc telluride (CZT) based detector system has been developed with the goal of combining molecular breast imaging (MBI) and magnetic resonance imaging (MRI) to address shortcomings of each modality. The CZT detector system is comprised of four CZT modules tiled in a $2\times 2$ array. Each module consists of 256 pixels ( $16\times 16$ , 2.4 mm pixels) and features a built-in ASIC and FPGA. A custom digital readout circuit board was designed to interface the four modules with a microcontroller to a data acquisition PC. The system was placed within the bore of a 3 T GE Discovery MR750 and imaging performance of each modality evaluated using both sequential and simultaneous imaging protocols. The mean energy resolution of the gamma camera both inside and outside the MRI is 7.3% at 140 keV. The maximum increase in the integral uniformity was 3% when using a gradient echo MRI sequence while the mean differential uniformity when inside the MRI increased by 1%. Spatial resolution varied in a predictable manner from 2.4 mm FWHM at the collimator face to 6.9 mm at 10 cm from the collimator. Performance of the 3 T GE Discovery MR750 using a 16-channel breast RF coil array was measured with and without the gamma camera present using a gradient echo and spoiled gradient echo imaging sequence. A realistic 99mTc-filled breast-like phantom containing two lesions (30:1 lesion to background ratio) was used to assess the feasibility of both serial and simultaneous hybrid imaging. Sequential imaging resulted in a reduction in MRI SNR of 70-80% and a further decrease of 93-98% was observed when performing simultaneous MR/scintigraphy imaging, likely a result of RF interference originating from the CZT detector modules and associated analog electronics. Co-registered scintigraphic and MRI images display negligible geometric distortion when imaged with both simultaneous and serial imaging modes, thus indicating the feasibility of combining MBI with breast MRI.

Single-Flux Quantum Readout Circuits for Photon-Number-Resolving Superconducting Nanowire Single-Photon Detectors

Superconducting nanowire single-photon detectors (SNSPDs) with series-parallel meander-type configurations are demonstrated to have photon-number-resolving capabilities and are expected to be used for an evaluation system of single-photon generators and/or an energy-resolved fast detector for a new-generation time-of-flight mass spectrometry. In this paper, we present the design, fabrication, and confirmation of correct operations of two kinds of single-flux-quantum (SFQ) digital readout circuits for an SNSPD with a series-parallel meander-type configuration. Assuming a six-parallel meander-type configuration, we designed: a six-level current discriminator using six different magnetically coupled DC/SFQ converter circuits; and a Δ-type A/D converter using a quasi-one-junction SQUID (QOS) comparator with an SFQ feedback loop. For the design of the magnetically coupled inputs, we used a 3-D inductance extraction program FastHenry and the designed circuits were fabricated using a HYPRES 4.5-kA/cm 2 Nb process and a National Institute of Advanced Industrial Science and Technology (AIST) standard 2.5-kA/cm 2 Nb process.

Measuring the mutual effects between a CZT detector and MRI for the development of a simultaneous MBI/MRI insert.

While mammography is the gold standard for breast cancer screening, it suffers from poor sensitivity in women with dense breast tissue. Both breast MRI and molecular breast imaging (MBI) have been used as secondary imaging techniques. However, breast MRI suffers from low specificity and low sensitivity in MBI. A CZT based detector system has been developed with the goal of simultaneous MBI/MRI imaging to address the shortcomings of each modality. The performance of each modality needs to be addressed separately and together. The CZT system is comprised of four Redlen CZT modules tiled in a 2x2 array. Each module consists of 256 pixels and feature a builtin on-board ASIC and FPGA. A custom digital readout circuit board was designed to interface the four modules with a microcontroller to a PC. MR images were acquired with a 3T GE Discovery MR750 and Hologic breast coils. A gradient echo imaging sequence was used for all image acquisitions. A tissue mimicking phantom with a plastic grid insert (1 cm spacing) was used to evaluate geometric accuracy with the CZT detectors in the MRI bore. The average distance between the grid markers was 1A}0.2cm indicating negligible geometric distortion. Field maps were generated with a uniform phantom to quantify the effect on magnetic field homogeneity. Early results indicate a significant distortion (~10ppm) in the magnetic field closest to the coil. Further analysis of the MR images will determine the extent of image quality degradation. A flood map of Tc-99m was acquired to evaluate and implement an energy correction map and a uniformity map. In the absence of a magnetic field, the mean energy resolution at 140keV was 6.3%. After fully characterizing the uniformity, geometric accuracy and sensitivity, the same metrics will be evaluated in the MRI bore.

A digital output readout circuit with substrate temperature and bias heating compensation for uncooled micro-bolometer infrared focal plane arrays

Uncooled micro-bolometer FPAs (focal plane arrays) are influenced by substrate temperature and bias heating effect seriously. When the substrate temperature of the FPA changes greatly, the output and the responsivity of the FPA will vary a lot, thus the images’ quality is poor without the substrate temperature and bias heating effect compensation. In this paper, a new substrate temperature compensation method is proposed, which is completed during analog-to-digital converting with a 12-bit ADC (analog-to-digital converter), and the bias heating effect is canceled by trimming blind bolometers with on-chip DAC (digital-to-analog converter). The simulation result presents the achievable substrate temperature compensation range is about 80K. The proposed structure has been adopted in a readout circuit and successfully fabricated with 0.5μm CMOS process. For normal temperature scene (300K), the digital output only changes 16% when the substrate temperature changes from 253K to 333K. And the equivalent analog output only changes 546.2mV with a 3.4V output swing. As a result, the scene DR (dynamic range) does not change rapidly along with the variation of the substrate temperature and the images’ quality is improved greatly.

Development of a fast readout circuit for matrices of binary pixel sensors

A fast digital readout circuit for binary pixel sensors is presented. The architecture is designed to cope with matrices of the order of ten thousands of pixels and it can be involved proficiently for sparse single-particle detection at variable frame-rates, with an upper-bound of 1 Mfps in case the sensed flux is lower than few tens of pixel per frame. These characteristics make the architecture suitable for a black and white imaging sensor in a weak source environment where accurate timing and extremely high frame rates are required. In this work we describe the key features of the architecture, then we present an application case where the readout implemented in a CMOS pixel detector has been used in an electron interference experiment.

A microbial fuel cell powering an all-digital piezoresistive wireless sensor system

Microbial fuel cells (MFCs) are energy sources, which generate electrical charge thanks to bacteria metabolism. We report on a full custom pressure wireless sensor node especially designed to operate with MFCs, comprising an ultra-low-power Impulse-Radio Ultra-Wide-Band Transmitter operating in the low 0–960 MHz band, a nanostructured piezoresistive pressure sensor connected to a discrete component digital read-out circuit, and an MFC energy supply system. The sensor device comprises an insulating matrix of polydimethylsiloxane and nanostructured multi-branched copper microparticles as conductive filler. Our prototype system comprises two MFCs connected in series to power both the UWB transmitter, which consumes 40 μW, and the read-out circuit. The two MFCs generate an open circuit voltage of 1.2 ± 0.1 V. Each MFC prototype has a total volume of 0.34 L and comprises two circular poly(methyl methacrylate) chambers (anode and cathode) separated by a cation exchange membrane. The paper reports measurements on a fully working prototype that enables the separate transmission of pressure information and MFC voltage level at the same time. The complete sensor node powered by the MFC, thanks to its nature can be located either in harsh environments where there is no connection to energy grids, or in environments where the MFC, hence the complete node, can self-sustain.

Two approaches to improve FPGA performance for the stereo camera of the Chang'E-1 satellite

This article outlines the design of the CCD Stereo Camera optical sensor on the Chang'E-1 (CE-1) satellite which was created for China's first Lunar Exploration Program. The camera was designed to acquire three-dimensional stereoscopic images of the lunar surface based upon three-line array photogrammetric theory. A frame transfer CCD with 1024x1024 pixels is used to build a particular three-line array sensor. One of the main parts of this article is the design methodologies for the digital hardware readout circuits of the particular three-line array sensor using FPGA. At the beginning of the project, advanced high performance devices were not available, and the available FPGA was ACTEL's anti-fuse type A1020B, which has limited speed performance and logical resources. The FPGA implementation therefore is supported by two novel approaches to resolve two problems due to the device limitations. The results of the on-board flight validate that the proposed methodologies were successful.

The front-end chip of the SuperB SVT detector

The asymmetric e+e− collider SuperB is designed to deliver a high luminosity, greater than 1036cm−2s−1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2MHz per strip, the efficiency of the digital readout remained above 99.8%.

Fast Charge to Pulse Width Converter for Monolith PET Detector

Currently both preclinical and clinical PET systems are built with pixilated, optically isolated scintillators. The use of optical isolators limits the achievable packing fraction for designs that use small crystals. No optical isolation is necessary in a monolithic scintillation crystal design hence the sensitivity is increased. The light distribution created by a high energy interaction in a monolithic scintillator can be readout by a SiPM-array to determine the 3-D position of the interaction. We have developed a digital pulse width modulation readout circuit that is able to readout many densely packed SiPM-arrays connected to monolithic scintillators. A monolithic scintillation detector requires simultaneous acquisition of the light distribution on multiple sensors unlike in a one-to-one optically isolated pixelated configuration. Therefore, pulse width modulation can reduce the readout complexity of the monolithic scintillation detector. The circuit gives an output signal with a pulse width linear to the incoming charge. Therefore, the circuit provides both timing and intensity information using just one digital line per channel. The charge to pulse-width conversion ratio of the circuit is adjustable (e.g., 33 ns/pC). The trigger jitters σ 41.2 ps between two channels. The PCB offers 8 channels and comes with additional features: The gain variation of a SiPM is compensated over a large temperature range by controlling the bias voltage. We measured from 15°C to 42°C, here it can bring the variation of a SiPM in gain from -21 ns/ °C to +3.8 ns/ °C or stabilizes the variation of the energy resolution between 18 and 20%.

A Digital Readout IC with Digital Offset Canceller for Capacitive Sensors

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-㎑ signal bandwidth and oversampling ratio (OSR) of 64, thus a 3 rd -order ΔΣ modulator operating at 1 ㎒ was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-㎛ CMOS mixed-mode process, and occupied 0.86 × 1.33 ㎟. The measurement results shows suppressed DC power under about -30 ㏈FS with minimized device flicker noise.

Demonstration of digital readout circuit for superconducting nanowire single photon detector

We demonstrate the transfer of single photon triggered electrical pulses from a superconducting nanowire single photon detector (SNSPD) to a single flux quantum (SFQ) pulse. We describe design and test of a digital SFQ based SNSPD readout circuit and demonstrate its correct operation. Both circuits (SNSPD and SFQ) operate under the same cryogenic conditions and are directly connected by wire bonds. A future integration of the present multi-chip configuration seems feasible because both fabrication process and materials are very similar. In contrast to commonly used semiconductor amplifiers, SFQ circuits combine very low power dissipation (a few microwatts) with very high operation speed, thus enabling count-rates of several gigahertz. The SFQ interface circuit simplifies the SNSPD readout and enables large numbers of detectors for future compact multi-pixel systems with single photon counting resolution. The demonstrated circuit has great potential for scaling the present interface solution to 1,000 detectors by using a single SFQ chip.

Development and simulation results of a sparsification and readout circuit for wide pixel matrices

In future collider experiments, the increasing luminosity and centre of mass energy are rising challenging problems in the design of new inner tracking systems. In this context we develop high-efficiency readout architectures for large binary pixel matrices that are meant to cope with the high-stressing conditions foreseen in the innermost layers of a tracker [The SuperB Conceptual Design Report, INFN/AE-07/02, SLAC-R-856, LAL 07-15, Available online at: http://www.pi.infn.it/SuperB ]. We model and design digital readout circuits to be integrated on VLSI ASICs. These architectures can be realized with different technology processes and sensors: they can be implemented on the same silicon sensor substrate of a CMOS MAPS devices (Monolithic Active Pixel Sensor), on the CMOS tier of a hybrid pixel sensor or in a 3D chip where the digital layer is stacked on the sensor and the analog layers [V. Re et al., Nuc. Instr. and Meth. in Phys. Res. A, doi:10.1016/j.nima.2010.05.039 ]. In the presented work, we consider a data-push architecture designed for a sensor matrix of an area of about 1.3 cm 2 with a pitch of 50 microns. The readout circuit tries to take great advantage of the high density of in-pixel digital logic allowed by vertical integration. We aim at sustaining a rate density of 100 Mtrack ⋅ s −1 ⋅ cm −2 with a temporal resolution below 1 μs . We show how this architecture can cope with these stressing conditions presenting the results of Monte Carlo simulations.