Power Amplifier Digital Predistortion Research Articles

A Block-Based LMS Using the Walsh Transform for Digital Predistortion of Power Amplifiers

A Block-Based LMS Using the Walsh Transform for Digital Predistortion of Power Amplifiers

A low complexity loop‐delay estimation algorithm based on sliding window for power amplifier characterization

AbstractIt is well known that accurate estimation of the loop delay between the input and output feedback signals is the key to behavioral modeling and digital predistortion of power amplifier. Nevertheless, most of the traditional loop‐delay compensation algorithms have the disadvantage of high computational complexity. For the purpose of solving this problem, a loop‐delay estimation algorithm based on sliding window has been proposed in this paper, where the first derivative characteristic of the signal is employed to evaluate the correlation between the input and output feedback signals. The simulation and experiment are carried out with different bandwidth signals in this paper. The results show that the proposed algorithm and the traditional cross‐correlation‐based method could align the input and output feedback signals successfully. But in terms of resource consumption, the proposed algorithm could reduce the multiplier nearly by 100% and the adder by approximately 93.2%.

A pruning method of feedforward neural network based on contribution of input components for digital predistortion of power amplifier

AbstractIn this paper, a pruning method based on contribution of input components is proposed to optimize the structure of Feedforward neural network (FNN) model for digital predistortion of power amplifier. The optimized hyperparameters are the specific input components. The pruning algorithm is divided into two stages. The stage I is used to rough rank the importance of input components and the stage II is used to modify the results of stage I. Then, we can get an importance ranking of input components. By deleting unimportant input components, a pruned FNN model with fewer input components can be obtained. Test results show that the proposed algorithm can greatly simplify the FNN model on the premise of ensuring the predistortion performance.

Signed Orthogonal Regressor Algorithm for Digital Predistortion of Power Amplifiers

Digital predistortion (DPD) of broadband power amplifiers (PAs) requires a large number of parameters to compensate for the severe nonlinear distortion, which may cause considerable computational complexity in the DPD parameter identification process. To solve this problem, we proposed a novel signed orthogonal regressor algorithm (SORA) to simplify the identification of DPD parameters. Based on the signed regressor algorithm and principal component analysis (PCA), the proposed algorithm can eliminate most of the multiplication operations in the identification process and greatly reduce the computational complexity. Furthermore, the proposed SORA is modified to be able to estimate each parameter independently. Experimental results show that compared with the conventional PCA-based method, the proposed two methods can realize comparable linearization performance with significantly lower computational complexity.

Augmented Iterative Learning Control for Neural-Network-Based Joint Crest Factor Reduction and Digital Predistortion of Power Amplifiers

Digital predistorsion (DPD) is a commonly used approach to compensate for the power amplifiers (PA) nonlinearities and memory effects as well as to improve its power efficiency. To alleviate the restriction brought by high peak-to-average power ratio (PAPR) of input signals, crest factor reduction (CFR) is needed for higher efficiency. In modern communication systems, power of transmitted signals gets lower, which makes complexities of CFR and DPD become nonnegligible. This article proposes a new approach to realize a joint CFR and DPD model using neural networks (NN). The modeling accuracy is guaranteed by a new proposed augmented iterative learning control (AILC) algorithm for the NN training signals. Compared with conventional ILC, the proposed AILC is shown more robust according to simulation and experimental results. The proposed AILC-based NN-CFRDPD is experimentally evaluated on different test benches.

Linear-Decomposition Digital Predistortion of Power Amplifiers for 5G Ultrabroadband Applications

This article proposes a novel linear-decomposition digital predistortion (LD-DPD) for the linearization of power amplifiers (PAs) in ultra broadband applications. LD-DPD is able to perform excellently with low complexity at the oversampling rate of only 1.5×. It combines leading terms with a linear decomposition of cross-terms, which can reduce the spectrum aliasing even when sampling rates are insufficient. The model complexity of the proposed model is quantified by floating-point operations. Experiments on broadband PAs at both sub-6-GHz and millimeter-wave frequencies have provided effective validations of the proposed model by employing the 5G New Radio (NR) waveforms. Particularly, the linearization of a signal with modulated bandwidth (BW) 800 MHz at 28 GHz was demonstrated. LD-DPD achieved a normalized root-mean-square error (NRMSE) of 3.34% for continuous 800-MHz modulated signal at the sampling rate of only 1.2 GHz. Compared with the already published DPDs, the proposed method is featured by high accuracy with limited available sampling rates to significantly reduce the system BW requirements. Also, it presents much lower complexity that will reduce expenses on hardware, which is very suitable for 5G ultra broadband applications.

Complex-Valued Pipelined Chebyshev Functional Link Recurrent Neural Network for Joint Compensation of Wideband Transmitter Distortions and Impairments

In this article, a novel digital predistortion (DPD) model based on complex-valued pipelined Chebyshev functional link recurrent neural network (CPCFLRNN) for joint compensation of wideband transmitter distortions and impairments is proposed. The functional link neural network (FLNN) model has attracted much attention from scholars, and many improved models using this structure, such as Chebyshev FLNN, have been applied in the DPD of power amplifiers (PAs). However, these existing neural network models cannot deal with complex-valued input signals simultaneously, and the real-valued model structure will introduce cumbersome training algorithm and result in a long training time. The pipelined recurrent neural network (PRNN) has been successfully applied to nonlinear signal prediction because of its excellent ability for dealing with nonlinear nonstationary signals. Therefore, the PRNN model containing Chebyshev structure is extended to complex domain for the first time to obtain the CPCFLRNN model for DPD application. Considering the strong correlation of in-phase and quadrature phase (I/Q) components of the transmitter signal, the real time recurrent learning (RTRL) algorithm based on fully complex activation function is selected and extended to complex domain to obtain the complex-valued RTRL (CRTRL) algorithm for CPCFLRNN model training. A GaN PA was employed to verify the effectiveness of the proposed models. And the input signal is a 30MHz LTE signals which consists of I/Q imbalance and dc offsets. The experimental results show that the proposed CPCFLRNN model have more accurate modeling effect and better linearization performance compared with the conventional DPD models.

Artificial techniques applied to the improvement of the previous signals in the power amplifiers

Abstract A rapid evolution in electronic systems has been experienced in recent years, and one of the fields where this development has been notorious is the telecommunication systems in which users demand more and better services and with higher data transfer speeds. This has generated the need to develop new devices, algorithms and systems that manage to satisfy the requirements demanded y new technologies. An example of the above is the front-end of telecommunication systems. Systems need to be more efficient, but some elements of the systems, as the power amplifier, present nonlinearity when operating in its most efficient region, causing that it has to make a commitment between efficiency and linearity. This paper presents a comparison of different artificial neural network architectures, as a behavioral modeling method, to perform digital predistortion of power amplifiers.

Model Identification for Digital Predistortion of Power Amplifier With Signed Regressor Algorithm

In this letter, a low-complexity approach is proposed to estimate model parameters of digital predistortion (DPD). It takes the advantage of low implementation cost of the signed regressor algorithm and eliminates most multiplications required. A Walsh–Hadamard transform is employed to avoid the correlation between signed DPD basis functions. Performance of the proposed approach is evaluated via experiments, with a two-carrier long term evolution-advanced signal on a 3.5-GHz power amplifier. It is shown that compared with the conventional least-square-based method the proposed approach can achieve similar linearization and convergence performance with much lower computational complexity.

A Novel Generalized Parallel Two-Box Structure for Behavior Modeling and Digital Predistortion of RF Power Amplifiers at LTE Applications

This paper presents a generalized parallel two-box structure that is proposed for modeling and digital predistortion of power amplifiers and wireless transmitters exhibiting memory effects. The proposed predistortion scheme consists of two separable boxes; the first is utilized to model the static behavior of the power amplifier, while the second is proposed to consider the memory effect and nonlinear distortion of the power amplifier. The coefficients of the proposed model are identified by applying an indirect learning structure and a least square method. The validation of the proposed model is carried out using the simulation of the power amplifier and the digital predistortion excited by a 64QAM signal in the advanced design system software. According to the simulation results, the criterion of adjacent channel power ratio reduced by about 16 dB. The simulation results reveal an adjacent channel power ratio of almost − 48 dB. Indeed, the proposed model leads to a better performance in terms of spectral regrowth in comparison with the memory polynomial model, and it also reduces the number of coefficients by approximately 22%. This proposed model enables a more accurate modeling of nonlinear distortion and memory effects compared to previous linearization methods.

Digital predistortion of power amplifiers using structured compressed‐sensing Volterra series

Digital predistortion has become an attractive technique for power amplifier linearisation whose limiting factor for using Volterra series as the underlying model is its computational complexity, since the number of components rapidly grows with the non-linear order and memory. Based on a previous reference algorithm, which consists on applying the orthogonal matching pursuit for the sorting of the model components and a Bayesian information criterion for the selection of the optimum number of components, a new technique to reduce the size of the support set taking into account the structural information within a model is presented. Experimental results of the predistortion of a commercial power amplifier are given as a proof of its capabilities, showing equivalent performance to the pruning with the reference algorithm while further reducing the number of components.

An Optimization Platform for Digital Predistortion of Power Amplifiers

The article introduces an integrated hardware/software codesign and test platform for the digital predistortion and power amplifier blocks of radiofrequency transceivers. The platform allows evaluation and optimization of system performance with minimum computational resources, contributing to higher design flexibility. The platform is demonstrated on a variety of power amplifiers.

Baseband Equivalent Volterra Series for Behavioral Modeling and Digital Predistortion of Power Amplifiers Driven With Wideband Carrier Aggregated Signals

This paper presents a new baseband equivalent (BBE) Volterra-series model suitable for the behavioral modeling and linearization of wideband RF power amplifiers (PAs). Starting with passband Volterra series, and following a number of signal transformations, a discrete expression relating the envelopes of the output and input signals to the carrier frequency was derived. The new BBE Volterra series reduces the number of kernels, and hence, avoids resorting to the pruning approaches commonly applied in the literature to the classical low-pass equivalent (LPE) Volterra formulation. The proposed baseband Volterra series has similar modeling and linearization performance to the full classical LPE Volterra series. It also outperforms the pruned LPE Volterra models, which use a dynamic deviation reduction approach, in terms of both linearization performance and complexity. The proposed BBE Volterra series was successfully used to linearize different PAs (200-W LDMOS Doherty and 45-W broadband GaN PA) driven with wideband and intra-band carrier aggregated signals (mixed LTE and WCDMA signals).

Novel Technique for Wideband Digital Predistortion of Power Amplifiers With an Under-Sampling ADC

Most conventional wideband digital predistortion (DPD) techniques require the use of a very high-speed analog-to- digital converter (ADC) in the feedback path. This paper proposes a novel technique, termed under-sampling restoration digital predistortion (USR-DPD), to linearize wideband power amplifiers (PAs) with ADCs that operate at sampling rates much lower than required by Nyquist limits for the predistorted band (under-sampling ADCs). The USR processing is implemented in an iterative way to restore full-band PA output information from the under-sampled output signal, allowing memory DPD models to be successfully extracted. The USR-DPD can operate in two modes: without and with a band-limiting filter in the feedback path. In comparison with conventional DPD techniques, the requirement for ADC sampling frequency can be significantly reduced using the USR-DPD approach. Experimental tests were realized for two PAs with numerous signals (10-, 20-, 40-, and 60-MHz long-term evolution signals) using different ADC sampling frequencies. The DPD with the under-sampling ADC could achieve comparable performances to its counterpart with a full-rate ADC, while using 3-5 times lower sampling frequency, and around -50-dBc adjacent channel power ratios were achieved.

Digital predistortion using modified dynamic deviation reduction‐based Volterra model

A modified dynamic deviation reduction-based Volterra (MDDRV) model is presented for digital predistortion of power amplifiers. The MDDRV model is a combination of the memory polynomial model and the DDRV model. The effectiveness of the MDDRV model is validated based on experimental results.

Digital predistortion of power amplifiers based on compound memory polynomial model

Digital predistortion of power amplifiers based on compound memory polynomial model

An accurate physical knowledge-based model for behavioral modeling and digital predistortion of power amplifiers

The objective of this article is to present an accurate model for behavioral modeling and digital predistortion of power amplifiers (PAs) using physical knowledge. Starting with the physically meaningful block model, we present a novel approach to simplify the block model and propose a simplified physical knowledge-based (SPK) model. The SPK model's performance was experimentally assessed by two types of PAs (a LDMOS Doherty PA and a GaN Doherty PA) and two signals (a single carrier 16QAM signal and a 2-carrier WCDMA signal). All experimental results prove the superiority of the SPK model. Compared with the 1st-dynamic deviation reduction (DDR) approach and the 2nd-simplified DDR approach, the SPK approach achieves average ACPR improvements of 4.4 dB and 2.5 dB, respectively. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE 23: 682–689, 2013.

Digital predistortion of power amplifiers using look-up table method with memory effects for LTE wireless systems

Abstract Digital predistortion (DPD) techniques are widely used to linearize of RF power amplifiers. In this article, a memory polynomial-based power has been modeled with memory order of 5 and nonlinearity order of 9. These specifications had been found suitable for advanced long-term evolution (LTE) wireless systems. A suitable DPD model was created based on the least square error minimization. Results for the complementary cumulative distribution function and normalized mean squared error were also computed. The adjacent channel leakage power ratio and error vector magnitude calculations showed that the proposed DPD for LTE system performed within the required limits as desired.

Twin Nonlinear Two-Box Models for Power Amplifiers and Transmitters Exhibiting Memory Effects With Application to Digital Predistortion

In this paper, a new class of models, named twin nonlinear two-box (TNTB) models, is proposed for modeling and digital predistortion of power amplifiers and transmitters exhibiting memory effects. The forward, reverse, and parallel TNTB models are introduced. These models enable a more general modeling of nonlinear distortions and memory effects in comparison with previously reported behavioural models. The models' performance is assessed experimentally for a high power Doherty amplifier driven by multi-carrier WCDMA signals. The modeling and predistortion results demonstrate the effectiveness of the proposed models when compared to the well established memory polynomials. Indeed, the proposed models lead to the same performance as memory polynomial models while reducing the number of parameters by approximately 50%. Definitely, only 24 parameters were required to accurately model and linearize a highly nonlinear Doherty power amplifier driven by a 20 MHz wide multi-carrier signal. To the best of the authors' knowledge, this is the lowest complexity model/digital predistorter reported for similar context.

Design and implementation of self-calibration for digital predistortion of power amplifiers

The linearization of Power Amplifiers (PAs) on mobile handsets is a critical problem for stringent systems such as WiMAX. In this paper we present the results of our investigation on the feasibility of self-calibration from a theoretical point of view as well as on a FPGA-based hardware platform for the predistortion of PAs. We propose a system design in three phases i) self-calibration, ii) inverse function calculation and iii) predistortion. MATLAB simulation results show that the functionality of the self-calibration, inverse function calculation and predistortion can linearize the PA characteristics and that the FPGA implementation results of the self-calibration are promising, paving the way for an efficient self-calibrating digital predistorter.